1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 /*! \file liquidio_common.h
19 * \brief Common: Structures and macros used in PCI-NIC package by core and
20 * host driver.
21 */
22
23 #ifndef __LIQUIDIO_COMMON_H__
24 #define __LIQUIDIO_COMMON_H__
25
26 #include "octeon_config.h"
27
28 #define LIQUIDIO_PACKAGE ""
29 #define LIQUIDIO_BASE_MAJOR_VERSION 1
30 #define LIQUIDIO_BASE_MINOR_VERSION 6
31 #define LIQUIDIO_BASE_MICRO_VERSION 1
32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
33 __stringify(LIQUIDIO_BASE_MINOR_VERSION)
34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \
36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \
37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \
38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION)
39
40 struct lio_version {
41 u16 major;
42 u16 minor;
43 u16 micro;
44 u16 reserved;
45 };
46
47 #define CONTROL_IQ 0
48 /** Tag types used by Octeon cores in its work. */
49 enum octeon_tag_type {
50 ORDERED_TAG = 0,
51 ATOMIC_TAG = 1,
52 NULL_TAG = 2,
53 NULL_NULL_TAG = 3
54 };
55
56 /* pre-defined host->NIC tag values */
57 #define LIO_CONTROL (0x11111110)
58 #define LIO_DATA(i) (0x11111111 + (i))
59
60 /* Opcodes used by host driver/apps to perform operations on the core.
61 * These are used to identify the major subsystem that the operation
62 * is for.
63 */
64 #define OPCODE_CORE 0 /* used for generic core operations */
65 #define OPCODE_NIC 1 /* used for NIC operations */
66 /* Subcodes are used by host driver/apps to identify the sub-operation
67 * for the core. They only need to by unique for a given subsystem.
68 */
69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
70
71 /** OPCODE_CORE subcodes. For future use. */
72
73 /** OPCODE_NIC subcodes */
74
75 /* This subcode is sent by core PCI driver to indicate cores are ready. */
76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01
77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */
78 #define OPCODE_NIC_CMD 0x03
79 #define OPCODE_NIC_INFO 0x04
80 #define OPCODE_NIC_PORT_STATS 0x05
81 #define OPCODE_NIC_MDIO45 0x06
82 #define OPCODE_NIC_TIMESTAMP 0x07
83 #define OPCODE_NIC_INTRMOD_CFG 0x08
84 #define OPCODE_NIC_IF_CFG 0x09
85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A
86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B
87 #define VF_DRV_LOADED 1
88 #define VF_DRV_REMOVED -1
89 #define VF_DRV_MACADDR_CHANGED 2
90
91 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5
92
93 /* Application codes advertised by the core driver initialization packet. */
94 #define CVM_DRV_APP_START 0x0
95 #define CVM_DRV_NO_APP 0
96 #define CVM_DRV_APP_COUNT 0x2
97 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0)
98 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1)
99 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2)
100 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1)
101
102 #define BYTES_PER_DHLEN_UNIT 8
103 #define MAX_REG_CNT 2000000U
104 #define INTRNAMSIZ 32
105 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ)
106 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2)
107 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2)
108
109 #define SCR2_BIT_FW_LOADED 63
110
incr_index(u32 index,u32 count,u32 max)111 static inline u32 incr_index(u32 index, u32 count, u32 max)
112 {
113 if ((index + count) >= max)
114 index = index + count - max;
115 else
116 index += count;
117
118 return index;
119 }
120
121 #define OCT_BOARD_NAME 32
122 #define OCT_SERIAL_LEN 64
123
124 /* Structure used by core driver to send indication that the Octeon
125 * application is ready.
126 */
127 struct octeon_core_setup {
128 u64 corefreq;
129
130 char boardname[OCT_BOARD_NAME];
131
132 char board_serial_number[OCT_SERIAL_LEN];
133
134 u64 board_rev_major;
135
136 u64 board_rev_minor;
137
138 };
139
140 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/
141
142 /* The Scatter-Gather List Entry. The scatter or gather component used with
143 * a Octeon input instruction has this format.
144 */
145 struct octeon_sg_entry {
146 /** The first 64 bit gives the size of data in each dptr.*/
147 union {
148 u16 size[4];
149 u64 size64;
150 } u;
151
152 /** The 4 dptr pointers for this entry. */
153 u64 ptr[4];
154
155 };
156
157 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry))
158
159 /* \brief Add size to gather list
160 * @param sg_entry scatter/gather entry
161 * @param size size to add
162 * @param pos position to add it.
163 */
add_sg_size(struct octeon_sg_entry * sg_entry,u16 size,u32 pos)164 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
165 u16 size,
166 u32 pos)
167 {
168 #ifdef __BIG_ENDIAN_BITFIELD
169 sg_entry->u.size[pos] = size;
170 #else
171 sg_entry->u.size[3 - pos] = size;
172 #endif
173 }
174
175 /*------------------------- End Scatter/Gather ---------------------------*/
176
177 #define OCTNET_FRM_LENGTH_SIZE 8
178
179 #define OCTNET_FRM_PTP_HEADER_SIZE 8
180
181 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */
182
183 #define OCTNET_MIN_FRM_SIZE 64
184
185 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE)
186
187 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE)
188
189 /** NIC Commands are sent using this Octeon Input Queue */
190 #define OCTNET_CMD_Q 0
191
192 /* NIC Command types */
193 #define OCTNET_CMD_CHANGE_MTU 0x1
194 #define OCTNET_CMD_CHANGE_MACADDR 0x2
195 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3
196 #define OCTNET_CMD_RX_CTL 0x4
197
198 #define OCTNET_CMD_SET_MULTI_LIST 0x5
199 #define OCTNET_CMD_CLEAR_STATS 0x6
200
201 /* command for setting the speed, duplex & autoneg */
202 #define OCTNET_CMD_SET_SETTINGS 0x7
203 #define OCTNET_CMD_SET_FLOW_CTL 0x8
204
205 #define OCTNET_CMD_MDIO_READ_WRITE 0x9
206 #define OCTNET_CMD_GPIO_ACCESS 0xA
207 #define OCTNET_CMD_LRO_ENABLE 0xB
208 #define OCTNET_CMD_LRO_DISABLE 0xC
209 #define OCTNET_CMD_SET_RSS 0xD
210 #define OCTNET_CMD_WRITE_SA 0xE
211 #define OCTNET_CMD_DELETE_SA 0xF
212 #define OCTNET_CMD_UPDATE_SA 0x12
213
214 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
215 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
216 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
217 #define OCTNET_CMD_VERBOSE_ENABLE 0x14
218 #define OCTNET_CMD_VERBOSE_DISABLE 0x15
219
220 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16
221 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17
222 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18
223 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19
224
225 #define OCTNET_CMD_ID_ACTIVE 0x1a
226
227 #define OCTNET_CMD_SET_UC_LIST 0x1b
228 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c
229
230 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f
231
232 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0
233 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1
234 #define OCTNET_CMD_RXCSUM_ENABLE 0x0
235 #define OCTNET_CMD_RXCSUM_DISABLE 0x1
236 #define OCTNET_CMD_TXCSUM_ENABLE 0x0
237 #define OCTNET_CMD_TXCSUM_DISABLE 0x1
238 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1
239 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0
240
241 #define LIO_CMD_WAIT_TM 100
242
243 /* RX(packets coming from wire) Checksum verification flags */
244 /* TCP/UDP csum */
245 #define CNNIC_L4SUM_VERIFIED 0x1
246 #define CNNIC_IPSUM_VERIFIED 0x2
247 #define CNNIC_TUN_CSUM_VERIFIED 0x4
248 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
249
250 /*LROIPV4 and LROIPV6 Flags*/
251 #define OCTNIC_LROIPV4 0x1
252 #define OCTNIC_LROIPV6 0x2
253
254 /* Interface flags communicated between host driver and core app. */
255 enum octnet_ifflags {
256 OCTNET_IFFLAG_PROMISC = 0x01,
257 OCTNET_IFFLAG_ALLMULTI = 0x02,
258 OCTNET_IFFLAG_MULTICAST = 0x04,
259 OCTNET_IFFLAG_BROADCAST = 0x08,
260 OCTNET_IFFLAG_UNICAST = 0x10
261 };
262
263 /* wqe
264 * --------------- 0
265 * | wqe word0-3 |
266 * --------------- 32
267 * | PCI IH |
268 * --------------- 40
269 * | RPTR |
270 * --------------- 48
271 * | PCI IRH |
272 * --------------- 56
273 * | OCT_NET_CMD |
274 * --------------- 64
275 * | Addtl 8-BData |
276 * | |
277 * ---------------
278 */
279
280 union octnet_cmd {
281 u64 u64;
282
283 struct {
284 #ifdef __BIG_ENDIAN_BITFIELD
285 u64 cmd:5;
286
287 u64 more:6; /* How many udd words follow the command */
288
289 u64 reserved:29;
290
291 u64 param1:16;
292
293 u64 param2:8;
294
295 #else
296
297 u64 param2:8;
298
299 u64 param1:16;
300
301 u64 reserved:29;
302
303 u64 more:6;
304
305 u64 cmd:5;
306
307 #endif
308 } s;
309
310 };
311
312 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd))
313
314 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */
315 #define LIO_SOFTCMDRESP_IH2 40
316 #define LIO_SOFTCMDRESP_IH3 (40 + 8)
317
318 #define LIO_PCICMD_O2 24
319 #define LIO_PCICMD_O3 (24 + 8)
320
321 /* Instruction Header(DPI) - for OCTEON-III models */
322 struct octeon_instr_ih3 {
323 #ifdef __BIG_ENDIAN_BITFIELD
324
325 /** Reserved3 */
326 u64 reserved3:1;
327
328 /** Gather indicator 1=gather*/
329 u64 gather:1;
330
331 /** Data length OR no. of entries in gather list */
332 u64 dlengsz:14;
333
334 /** Front Data size */
335 u64 fsz:6;
336
337 /** Reserved2 */
338 u64 reserved2:4;
339
340 /** PKI port kind - PKIND */
341 u64 pkind:6;
342
343 /** Reserved1 */
344 u64 reserved1:32;
345
346 #else
347 /** Reserved1 */
348 u64 reserved1:32;
349
350 /** PKI port kind - PKIND */
351 u64 pkind:6;
352
353 /** Reserved2 */
354 u64 reserved2:4;
355
356 /** Front Data size */
357 u64 fsz:6;
358
359 /** Data length OR no. of entries in gather list */
360 u64 dlengsz:14;
361
362 /** Gather indicator 1=gather*/
363 u64 gather:1;
364
365 /** Reserved3 */
366 u64 reserved3:1;
367
368 #endif
369 };
370
371 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */
372 /** BIG ENDIAN format. */
373 struct octeon_instr_pki_ih3 {
374 #ifdef __BIG_ENDIAN_BITFIELD
375
376 /** Wider bit */
377 u64 w:1;
378
379 /** Raw mode indicator 1 = RAW */
380 u64 raw:1;
381
382 /** Use Tag */
383 u64 utag:1;
384
385 /** Use QPG */
386 u64 uqpg:1;
387
388 /** Reserved2 */
389 u64 reserved2:1;
390
391 /** Parse Mode */
392 u64 pm:3;
393
394 /** Skip Length */
395 u64 sl:8;
396
397 /** Use Tag Type */
398 u64 utt:1;
399
400 /** Tag type */
401 u64 tagtype:2;
402
403 /** Reserved1 */
404 u64 reserved1:2;
405
406 /** QPG Value */
407 u64 qpg:11;
408
409 /** Tag Value */
410 u64 tag:32;
411
412 #else
413
414 /** Tag Value */
415 u64 tag:32;
416
417 /** QPG Value */
418 u64 qpg:11;
419
420 /** Reserved1 */
421 u64 reserved1:2;
422
423 /** Tag type */
424 u64 tagtype:2;
425
426 /** Use Tag Type */
427 u64 utt:1;
428
429 /** Skip Length */
430 u64 sl:8;
431
432 /** Parse Mode */
433 u64 pm:3;
434
435 /** Reserved2 */
436 u64 reserved2:1;
437
438 /** Use QPG */
439 u64 uqpg:1;
440
441 /** Use Tag */
442 u64 utag:1;
443
444 /** Raw mode indicator 1 = RAW */
445 u64 raw:1;
446
447 /** Wider bit */
448 u64 w:1;
449 #endif
450
451 };
452
453 /** Instruction Header */
454 struct octeon_instr_ih2 {
455 #ifdef __BIG_ENDIAN_BITFIELD
456 /** Raw mode indicator 1 = RAW */
457 u64 raw:1;
458
459 /** Gather indicator 1=gather*/
460 u64 gather:1;
461
462 /** Data length OR no. of entries in gather list */
463 u64 dlengsz:14;
464
465 /** Front Data size */
466 u64 fsz:6;
467
468 /** Packet Order / Work Unit selection (1 of 8)*/
469 u64 qos:3;
470
471 /** Core group selection (1 of 16) */
472 u64 grp:4;
473
474 /** Short Raw Packet Indicator 1=short raw pkt */
475 u64 rs:1;
476
477 /** Tag type */
478 u64 tagtype:2;
479
480 /** Tag Value */
481 u64 tag:32;
482 #else
483 /** Tag Value */
484 u64 tag:32;
485
486 /** Tag type */
487 u64 tagtype:2;
488
489 /** Short Raw Packet Indicator 1=short raw pkt */
490 u64 rs:1;
491
492 /** Core group selection (1 of 16) */
493 u64 grp:4;
494
495 /** Packet Order / Work Unit selection (1 of 8)*/
496 u64 qos:3;
497
498 /** Front Data size */
499 u64 fsz:6;
500
501 /** Data length OR no. of entries in gather list */
502 u64 dlengsz:14;
503
504 /** Gather indicator 1=gather*/
505 u64 gather:1;
506
507 /** Raw mode indicator 1 = RAW */
508 u64 raw:1;
509 #endif
510 };
511
512 /** Input Request Header */
513 struct octeon_instr_irh {
514 #ifdef __BIG_ENDIAN_BITFIELD
515 u64 opcode:4;
516 u64 rflag:1;
517 u64 subcode:7;
518 u64 vlan:12;
519 u64 priority:3;
520 u64 reserved:5;
521 u64 ossp:32; /* opcode/subcode specific parameters */
522 #else
523 u64 ossp:32; /* opcode/subcode specific parameters */
524 u64 reserved:5;
525 u64 priority:3;
526 u64 vlan:12;
527 u64 subcode:7;
528 u64 rflag:1;
529 u64 opcode:4;
530 #endif
531 };
532
533 /** Return Data Parameters */
534 struct octeon_instr_rdp {
535 #ifdef __BIG_ENDIAN_BITFIELD
536 u64 reserved:49;
537 u64 pcie_port:3;
538 u64 rlen:12;
539 #else
540 u64 rlen:12;
541 u64 pcie_port:3;
542 u64 reserved:49;
543 #endif
544 };
545
546 /** Receive Header */
547 union octeon_rh {
548 #ifdef __BIG_ENDIAN_BITFIELD
549 u64 u64;
550 struct {
551 u64 opcode:4;
552 u64 subcode:8;
553 u64 len:3; /** additional 64-bit words */
554 u64 reserved:17;
555 u64 ossp:32; /** opcode/subcode specific parameters */
556 } r;
557 struct {
558 u64 opcode:4;
559 u64 subcode:8;
560 u64 len:3; /** additional 64-bit words */
561 u64 extra:28;
562 u64 vlan:12;
563 u64 priority:3;
564 u64 csum_verified:3; /** checksum verified. */
565 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */
566 u64 encap_on:1;
567 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
568 } r_dh;
569 struct {
570 u64 opcode:4;
571 u64 subcode:8;
572 u64 len:3; /** additional 64-bit words */
573 u64 reserved:11;
574 u64 num_gmx_ports:8;
575 u64 max_nic_ports:10;
576 u64 app_cap_flags:4;
577 u64 app_mode:8;
578 u64 pkind:8;
579 } r_core_drv_init;
580 struct {
581 u64 opcode:4;
582 u64 subcode:8;
583 u64 len:3; /** additional 64-bit words */
584 u64 reserved:8;
585 u64 extra:25;
586 u64 gmxport:16;
587 } r_nic_info;
588 #else
589 u64 u64;
590 struct {
591 u64 ossp:32; /** opcode/subcode specific parameters */
592 u64 reserved:17;
593 u64 len:3; /** additional 64-bit words */
594 u64 subcode:8;
595 u64 opcode:4;
596 } r;
597 struct {
598 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */
599 u64 encap_on:1;
600 u64 has_hwtstamp:1; /** 1 = has hwtstamp */
601 u64 csum_verified:3; /** checksum verified. */
602 u64 priority:3;
603 u64 vlan:12;
604 u64 extra:28;
605 u64 len:3; /** additional 64-bit words */
606 u64 subcode:8;
607 u64 opcode:4;
608 } r_dh;
609 struct {
610 u64 pkind:8;
611 u64 app_mode:8;
612 u64 app_cap_flags:4;
613 u64 max_nic_ports:10;
614 u64 num_gmx_ports:8;
615 u64 reserved:11;
616 u64 len:3; /** additional 64-bit words */
617 u64 subcode:8;
618 u64 opcode:4;
619 } r_core_drv_init;
620 struct {
621 u64 gmxport:16;
622 u64 extra:25;
623 u64 reserved:8;
624 u64 len:3; /** additional 64-bit words */
625 u64 subcode:8;
626 u64 opcode:4;
627 } r_nic_info;
628 #endif
629 };
630
631 #define OCT_RH_SIZE (sizeof(union octeon_rh))
632
633 union octnic_packet_params {
634 u32 u32;
635 struct {
636 #ifdef __BIG_ENDIAN_BITFIELD
637 u32 reserved:24;
638 u32 ip_csum:1; /* Perform IP header checksum(s) */
639 /* Perform Outer transport header checksum */
640 u32 transport_csum:1;
641 /* Find tunnel, and perform transport csum. */
642 u32 tnl_csum:1;
643 u32 tsflag:1; /* Timestamp this packet */
644 u32 ipsec_ops:4; /* IPsec operation */
645 #else
646 u32 ipsec_ops:4;
647 u32 tsflag:1;
648 u32 tnl_csum:1;
649 u32 transport_csum:1;
650 u32 ip_csum:1;
651 u32 reserved:24;
652 #endif
653 } s;
654 };
655
656 /** Status of a RGMII Link on Octeon as seen by core driver. */
657 union oct_link_status {
658 u64 u64;
659
660 struct {
661 #ifdef __BIG_ENDIAN_BITFIELD
662 u64 duplex:8;
663 u64 mtu:16;
664 u64 speed:16;
665 u64 link_up:1;
666 u64 autoneg:1;
667 u64 if_mode:5;
668 u64 pause:1;
669 u64 flashing:1;
670 u64 reserved:15;
671 #else
672 u64 reserved:15;
673 u64 flashing:1;
674 u64 pause:1;
675 u64 if_mode:5;
676 u64 autoneg:1;
677 u64 link_up:1;
678 u64 speed:16;
679 u64 mtu:16;
680 u64 duplex:8;
681 #endif
682 } s;
683 };
684
685 /** The txpciq info passed to host from the firmware */
686
687 union oct_txpciq {
688 u64 u64;
689
690 struct {
691 #ifdef __BIG_ENDIAN_BITFIELD
692 u64 q_no:8;
693 u64 port:8;
694 u64 pkind:6;
695 u64 use_qpg:1;
696 u64 qpg:11;
697 u64 reserved:30;
698 #else
699 u64 reserved:30;
700 u64 qpg:11;
701 u64 use_qpg:1;
702 u64 pkind:6;
703 u64 port:8;
704 u64 q_no:8;
705 #endif
706 } s;
707 };
708
709 /** The rxpciq info passed to host from the firmware */
710
711 union oct_rxpciq {
712 u64 u64;
713
714 struct {
715 #ifdef __BIG_ENDIAN_BITFIELD
716 u64 q_no:8;
717 u64 reserved:56;
718 #else
719 u64 reserved:56;
720 u64 q_no:8;
721 #endif
722 } s;
723 };
724
725 /** Information for a OCTEON ethernet interface shared between core & host. */
726 struct oct_link_info {
727 union oct_link_status link;
728 u64 hw_addr;
729
730 #ifdef __BIG_ENDIAN_BITFIELD
731 u64 gmxport:16;
732 u64 macaddr_is_admin_asgnd:1;
733 u64 rsvd:31;
734 u64 num_txpciq:8;
735 u64 num_rxpciq:8;
736 #else
737 u64 num_rxpciq:8;
738 u64 num_txpciq:8;
739 u64 rsvd:31;
740 u64 macaddr_is_admin_asgnd:1;
741 u64 gmxport:16;
742 #endif
743
744 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF];
745 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF];
746 };
747
748 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info))
749
750 struct liquidio_if_cfg_info {
751 u64 iqmask; /** mask for IQs enabled for the port */
752 u64 oqmask; /** mask for OQs enabled for the port */
753 struct oct_link_info linfo; /** initial link information */
754 char liquidio_firmware_version[32];
755 };
756
757 /** Stats for each NIC port in RX direction. */
758 struct nic_rx_stats {
759 /* link-level stats */
760 u64 total_rcvd;
761 u64 bytes_rcvd;
762 u64 total_bcst;
763 u64 total_mcst;
764 u64 runts;
765 u64 ctl_rcvd;
766 u64 fifo_err; /* Accounts for over/under-run of buffers */
767 u64 dmac_drop;
768 u64 fcs_err;
769 u64 jabber_err;
770 u64 l2_err;
771 u64 frame_err;
772
773 /* firmware stats */
774 u64 fw_total_rcvd;
775 u64 fw_total_fwd;
776 u64 fw_total_fwd_bytes;
777 u64 fw_err_pko;
778 u64 fw_err_link;
779 u64 fw_err_drop;
780 u64 fw_rx_vxlan;
781 u64 fw_rx_vxlan_err;
782
783 /* LRO */
784 u64 fw_lro_pkts; /* Number of packets that are LROed */
785 u64 fw_lro_octs; /* Number of octets that are LROed */
786 u64 fw_total_lro; /* Number of LRO packets formed */
787 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
788 u64 fw_lro_aborts_port;
789 u64 fw_lro_aborts_seq;
790 u64 fw_lro_aborts_tsval;
791 u64 fw_lro_aborts_timer;
792 /* intrmod: packet forward rate */
793 u64 fwd_rate;
794 };
795
796 /** Stats for each NIC port in RX direction. */
797 struct nic_tx_stats {
798 /* link-level stats */
799 u64 total_pkts_sent;
800 u64 total_bytes_sent;
801 u64 mcast_pkts_sent;
802 u64 bcast_pkts_sent;
803 u64 ctl_sent;
804 u64 one_collision_sent; /* Packets sent after one collision*/
805 u64 multi_collision_sent; /* Packets sent after multiple collision*/
806 u64 max_collision_fail; /* Packets not sent due to max collisions */
807 u64 max_deferral_fail; /* Packets not sent due to max deferrals */
808 u64 fifo_err; /* Accounts for over/under-run of buffers */
809 u64 runts;
810 u64 total_collisions; /* Total number of collisions detected */
811
812 /* firmware stats */
813 u64 fw_total_sent;
814 u64 fw_total_fwd;
815 u64 fw_total_fwd_bytes;
816 u64 fw_err_pko;
817 u64 fw_err_link;
818 u64 fw_err_drop;
819 u64 fw_err_tso;
820 u64 fw_tso; /* number of tso requests */
821 u64 fw_tso_fwd; /* number of packets segmented in tso */
822 u64 fw_tx_vxlan;
823 u64 fw_err_pki;
824 };
825
826 struct oct_link_stats {
827 struct nic_rx_stats fromwire;
828 struct nic_tx_stats fromhost;
829
830 };
831
opcode_slow_path(union octeon_rh * rh)832 static inline int opcode_slow_path(union octeon_rh *rh)
833 {
834 u16 subcode1, subcode2;
835
836 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode);
837 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA);
838
839 return (subcode2 != subcode1);
840 }
841
842 #define LIO68XX_LED_CTRL_ADDR 0x3501
843 #define LIO68XX_LED_CTRL_CFGON 0x1f
844 #define LIO68XX_LED_CTRL_CFGOFF 0x100
845 #define LIO68XX_LED_BEACON_ADDR 0x3508
846 #define LIO68XX_LED_BEACON_CFGON 0x47fd
847 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
848 #define VITESSE_PHY_GPIO_DRIVEON 0x1
849 #define VITESSE_PHY_GPIO_CFG 0x8
850 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
851 #define VITESSE_PHY_GPIO_HIGH 0x2
852 #define VITESSE_PHY_GPIO_LOW 0x3
853 #define LED_IDENTIFICATION_ON 0x1
854 #define LED_IDENTIFICATION_OFF 0x0
855
856 struct oct_mdio_cmd {
857 u64 op;
858 u64 mdio_addr;
859 u64 value1;
860 u64 value2;
861 u64 value3;
862 };
863
864 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats))
865
866 struct oct_intrmod_cfg {
867 u64 rx_enable;
868 u64 tx_enable;
869 u64 check_intrvl;
870 u64 maxpkt_ratethr;
871 u64 minpkt_ratethr;
872 u64 rx_maxcnt_trigger;
873 u64 rx_mincnt_trigger;
874 u64 rx_maxtmr_trigger;
875 u64 rx_mintmr_trigger;
876 u64 tx_mincnt_trigger;
877 u64 tx_maxcnt_trigger;
878 u64 rx_frames;
879 u64 tx_frames;
880 u64 rx_usecs;
881 };
882
883 #define BASE_QUEUE_NOT_REQUESTED 65535
884
885 union oct_nic_if_cfg {
886 u64 u64;
887 struct {
888 #ifdef __BIG_ENDIAN_BITFIELD
889 u64 base_queue:16;
890 u64 num_iqueues:16;
891 u64 num_oqueues:16;
892 u64 gmx_port_id:8;
893 u64 vf_id:8;
894 #else
895 u64 vf_id:8;
896 u64 gmx_port_id:8;
897 u64 num_oqueues:16;
898 u64 num_iqueues:16;
899 u64 base_queue:16;
900 #endif
901 } s;
902 };
903
904 #endif
905