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1/*
2 * Copyright (c) 2016 Andreas Färber
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include "meson-gx.dtsi"
44#include <dt-bindings/gpio/meson-gxbb-gpio.h>
45#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46#include <dt-bindings/clock/gxbb-clkc.h>
47#include <dt-bindings/clock/gxbb-aoclkc.h>
48#include <dt-bindings/reset/gxbb-aoclkc.h>
49
50/ {
51	compatible = "amlogic,meson-gxbb";
52
53	soc {
54		usb0_phy: phy@c0000000 {
55			compatible = "amlogic,meson-gxbb-usb2-phy";
56			#phy-cells = <0>;
57			reg = <0x0 0xc0000000 0x0 0x20>;
58			resets = <&reset RESET_USB_OTG>;
59			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
60			clock-names = "usb_general", "usb";
61			status = "disabled";
62		};
63
64		usb1_phy: phy@c0000020 {
65			compatible = "amlogic,meson-gxbb-usb2-phy";
66			#phy-cells = <0>;
67			reg = <0x0 0xc0000020 0x0 0x20>;
68			resets = <&reset RESET_USB_OTG>;
69			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
70			clock-names = "usb_general", "usb";
71			status = "disabled";
72		};
73
74		usb0: usb@c9000000 {
75			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
76			reg = <0x0 0xc9000000 0x0 0x40000>;
77			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
78			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
79			clock-names = "otg";
80			phys = <&usb0_phy>;
81			phy-names = "usb2-phy";
82			dr_mode = "host";
83			status = "disabled";
84		};
85
86		usb1: usb@c9100000 {
87			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
88			reg = <0x0 0xc9100000 0x0 0x40000>;
89			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
90			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
91			clock-names = "otg";
92			phys = <&usb1_phy>;
93			phy-names = "usb2-phy";
94			dr_mode = "host";
95			status = "disabled";
96		};
97	};
98};
99
100&aobus {
101	pinctrl_aobus: pinctrl@14 {
102		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
103		#address-cells = <2>;
104		#size-cells = <2>;
105		ranges;
106
107		gpio_ao: bank@14 {
108			reg = <0x0 0x00014 0x0 0x8>,
109			      <0x0 0x0002c 0x0 0x4>,
110			      <0x0 0x00024 0x0 0x8>;
111			reg-names = "mux", "pull", "gpio";
112			gpio-controller;
113			#gpio-cells = <2>;
114			gpio-ranges = <&pinctrl_aobus 0 0 14>;
115		};
116
117		uart_ao_a_pins: uart_ao_a {
118			mux {
119				groups = "uart_tx_ao_a", "uart_rx_ao_a";
120				function = "uart_ao";
121			};
122		};
123
124		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
125			mux {
126				groups = "uart_cts_ao_a",
127				       "uart_rts_ao_a";
128				function = "uart_ao";
129			};
130		};
131
132		uart_ao_b_pins: uart_ao_b {
133			mux {
134				groups = "uart_tx_ao_b", "uart_rx_ao_b";
135				function = "uart_ao_b";
136			};
137		};
138
139		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
140			mux {
141				groups = "uart_cts_ao_b",
142				       "uart_rts_ao_b";
143				function = "uart_ao_b";
144			};
145		};
146
147		remote_input_ao_pins: remote_input_ao {
148			mux {
149				groups = "remote_input_ao";
150				function = "remote_input_ao";
151			};
152		};
153
154		i2c_ao_pins: i2c_ao {
155			mux {
156				groups = "i2c_sck_ao",
157				       "i2c_sda_ao";
158				function = "i2c_ao";
159			};
160		};
161
162		pwm_ao_a_3_pins: pwm_ao_a_3 {
163			mux {
164				groups = "pwm_ao_a_3";
165				function = "pwm_ao_a_3";
166			};
167		};
168
169		pwm_ao_a_6_pins: pwm_ao_a_6 {
170			mux {
171				groups = "pwm_ao_a_6";
172				function = "pwm_ao_a_6";
173			};
174		};
175
176		pwm_ao_a_12_pins: pwm_ao_a_12 {
177			mux {
178				groups = "pwm_ao_a_12";
179				function = "pwm_ao_a_12";
180			};
181		};
182
183		pwm_ao_b_pins: pwm_ao_b {
184			mux {
185				groups = "pwm_ao_b";
186				function = "pwm_ao_b";
187			};
188		};
189
190		i2s_am_clk_pins: i2s_am_clk {
191			mux {
192				groups = "i2s_am_clk";
193				function = "i2s_out_ao";
194			};
195		};
196
197		i2s_out_ao_clk_pins: i2s_out_ao_clk {
198			mux {
199				groups = "i2s_out_ao_clk";
200				function = "i2s_out_ao";
201			};
202		};
203
204		i2s_out_lr_clk_pins: i2s_out_lr_clk {
205			mux {
206				groups = "i2s_out_lr_clk";
207				function = "i2s_out_ao";
208			};
209		};
210
211		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
212			mux {
213				groups = "i2s_out_ch01_ao";
214				function = "i2s_out_ao";
215			};
216		};
217
218		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
219			mux {
220				groups = "i2s_out_ch23_ao";
221				function = "i2s_out_ao";
222			};
223		};
224
225		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
226			mux {
227				groups = "i2s_out_ch45_ao";
228				function = "i2s_out_ao";
229			};
230		};
231
232		spdif_out_ao_6_pins: spdif_out_ao_6 {
233			mux {
234				groups = "spdif_out_ao_6";
235				function = "spdif_out_ao";
236			};
237		};
238
239		spdif_out_ao_13_pins: spdif_out_ao_13 {
240			mux {
241				groups = "spdif_out_ao_13";
242				function = "spdif_out_ao";
243			};
244		};
245
246		ao_cec_pins: ao_cec {
247			mux {
248				groups = "ao_cec";
249				function = "cec_ao";
250			};
251		};
252
253		ee_cec_pins: ee_cec {
254			mux {
255				groups = "ee_cec";
256				function = "cec_ao";
257			};
258		};
259	};
260};
261
262&apb {
263	mali: gpu@c0000 {
264		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
265		reg = <0x0 0xc0000 0x0 0x40000>;
266		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
267			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
268			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
269			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
270			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
271			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
272			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
273			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
274			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
275			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
276		interrupt-names = "gp", "gpmmu", "pp", "pmu",
277			"pp0", "ppmmu0", "pp1", "ppmmu1",
278			"pp2", "ppmmu2";
279		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
280		clock-names = "bus", "core";
281
282		/*
283		 * Mali clocking is provided by two identical clock paths
284		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
285		 * free mux to safely change frequency while running.
286		 */
287		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
288				  <&clkc CLKID_MALI_0>,
289				  <&clkc CLKID_MALI>; /* Glitch free mux */
290		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
291					 <0>, /* Do Nothing */
292					 <&clkc CLKID_MALI_0>;
293		assigned-clock-rates = <0>, /* Do Nothing */
294				       <666666666>,
295				       <0>; /* Do Nothing */
296	};
297};
298
299&cbus {
300	spifc: spi@8c80 {
301		compatible = "amlogic,meson-gxbb-spifc";
302		reg = <0x0 0x08c80 0x0 0x80>;
303		#address-cells = <1>;
304		#size-cells = <0>;
305		clocks = <&clkc CLKID_SPI>;
306		status = "disabled";
307	};
308};
309
310&cec_AO {
311	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
312	clock-names = "core";
313};
314
315&clkc_AO {
316	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
317};
318
319&ethmac {
320	clocks = <&clkc CLKID_ETH>,
321		 <&clkc CLKID_FCLK_DIV2>,
322		 <&clkc CLKID_MPLL2>;
323	clock-names = "stmmaceth", "clkin0", "clkin1";
324};
325
326&hdmi_tx {
327	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
328	resets = <&reset RESET_HDMITX_CAPB3>,
329		 <&reset RESET_HDMI_SYSTEM_RESET>,
330		 <&reset RESET_HDMI_TX>;
331	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
332	clocks = <&clkc CLKID_HDMI_PCLK>,
333		 <&clkc CLKID_CLK81>,
334		 <&clkc CLKID_GCLK_VENCI_INT0>;
335	clock-names = "isfr", "iahb", "venci";
336};
337
338&hiubus {
339	clkc: clock-controller@0 {
340		compatible = "amlogic,gxbb-clkc";
341		#clock-cells = <1>;
342		reg = <0x0 0x0 0x0 0x3db>;
343	};
344};
345
346&hwrng {
347	clocks = <&clkc CLKID_RNG0>;
348	clock-names = "core";
349};
350
351&i2c_A {
352	clocks = <&clkc CLKID_I2C>;
353};
354
355&i2c_AO {
356	clocks = <&clkc CLKID_AO_I2C>;
357};
358
359&i2c_B {
360	clocks = <&clkc CLKID_I2C>;
361};
362
363&i2c_C {
364	clocks = <&clkc CLKID_I2C>;
365};
366
367&periphs {
368	pinctrl_periphs: pinctrl@4b0 {
369		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
370		#address-cells = <2>;
371		#size-cells = <2>;
372		ranges;
373
374		gpio: bank@4b0 {
375			reg = <0x0 0x004b0 0x0 0x28>,
376			      <0x0 0x004e8 0x0 0x14>,
377			      <0x0 0x00520 0x0 0x14>,
378			      <0x0 0x00430 0x0 0x40>;
379			reg-names = "mux", "pull", "pull-enable", "gpio";
380			gpio-controller;
381			#gpio-cells = <2>;
382			gpio-ranges = <&pinctrl_periphs 0 14 120>;
383		};
384
385		emmc_pins: emmc {
386			mux {
387				groups = "emmc_nand_d07",
388				       "emmc_cmd",
389				       "emmc_clk",
390				       "emmc_ds";
391				function = "emmc";
392			};
393		};
394
395		emmc_clk_gate_pins: emmc_clk_gate {
396			mux {
397				groups = "BOOT_8";
398				function = "gpio_periphs";
399			};
400			cfg-pull-down {
401				pins = "BOOT_8";
402				bias-pull-down;
403			};
404		};
405
406		nor_pins: nor {
407			mux {
408				groups = "nor_d",
409				       "nor_q",
410				       "nor_c",
411				       "nor_cs";
412				function = "nor";
413			};
414		};
415
416		spi_pins: spi-pins {
417			mux {
418				groups = "spi_miso",
419					"spi_mosi",
420					"spi_sclk";
421				function = "spi";
422			};
423		};
424
425		spi_ss0_pins: spi-ss0 {
426			mux {
427				groups = "spi_ss0";
428				function = "spi";
429			};
430		};
431
432		sdcard_pins: sdcard {
433			mux {
434				groups = "sdcard_d0",
435				       "sdcard_d1",
436				       "sdcard_d2",
437				       "sdcard_d3",
438				       "sdcard_cmd",
439				       "sdcard_clk";
440				function = "sdcard";
441			};
442		};
443
444		sdcard_clk_gate_pins: sdcard_clk_gate {
445			mux {
446				groups = "CARD_2";
447				function = "gpio_periphs";
448			};
449			cfg-pull-down {
450				pins = "CARD_2";
451				bias-pull-down;
452			};
453		};
454
455		sdio_pins: sdio {
456			mux {
457				groups = "sdio_d0",
458				       "sdio_d1",
459				       "sdio_d2",
460				       "sdio_d3",
461				       "sdio_cmd",
462				       "sdio_clk";
463				function = "sdio";
464			};
465		};
466
467		sdio_clk_gate_pins: sdio_clk_gate {
468			mux {
469				groups = "GPIOX_4";
470				function = "gpio_periphs";
471			};
472			cfg-pull-down {
473				pins = "GPIOX_4";
474				bias-pull-down;
475			};
476		};
477
478		sdio_irq_pins: sdio_irq {
479			mux {
480				groups = "sdio_irq";
481				function = "sdio";
482			};
483		};
484
485		uart_a_pins: uart_a {
486			mux {
487				groups = "uart_tx_a",
488				       "uart_rx_a";
489				function = "uart_a";
490			};
491		};
492
493		uart_a_cts_rts_pins: uart_a_cts_rts {
494			mux {
495				groups = "uart_cts_a",
496				       "uart_rts_a";
497				function = "uart_a";
498			};
499		};
500
501		uart_b_pins: uart_b {
502			mux {
503				groups = "uart_tx_b",
504				       "uart_rx_b";
505				function = "uart_b";
506			};
507		};
508
509		uart_b_cts_rts_pins: uart_b_cts_rts {
510			mux {
511				groups = "uart_cts_b",
512				       "uart_rts_b";
513				function = "uart_b";
514			};
515		};
516
517		uart_c_pins: uart_c {
518			mux {
519				groups = "uart_tx_c",
520				       "uart_rx_c";
521				function = "uart_c";
522			};
523		};
524
525		uart_c_cts_rts_pins: uart_c_cts_rts {
526			mux {
527				groups = "uart_cts_c",
528				       "uart_rts_c";
529				function = "uart_c";
530			};
531		};
532
533		i2c_a_pins: i2c_a {
534			mux {
535				groups = "i2c_sck_a",
536				       "i2c_sda_a";
537				function = "i2c_a";
538			};
539		};
540
541		i2c_b_pins: i2c_b {
542			mux {
543				groups = "i2c_sck_b",
544				       "i2c_sda_b";
545				function = "i2c_b";
546			};
547		};
548
549		i2c_c_pins: i2c_c {
550			mux {
551				groups = "i2c_sck_c",
552				       "i2c_sda_c";
553				function = "i2c_c";
554			};
555		};
556
557		eth_rgmii_pins: eth-rgmii {
558			mux {
559				groups = "eth_mdio",
560				       "eth_mdc",
561				       "eth_clk_rx_clk",
562				       "eth_rx_dv",
563				       "eth_rxd0",
564				       "eth_rxd1",
565				       "eth_rxd2",
566				       "eth_rxd3",
567				       "eth_rgmii_tx_clk",
568				       "eth_tx_en",
569				       "eth_txd0",
570				       "eth_txd1",
571				       "eth_txd2",
572				       "eth_txd3";
573				function = "eth";
574			};
575		};
576
577		eth_rmii_pins: eth-rmii {
578			mux {
579				groups = "eth_mdio",
580				       "eth_mdc",
581				       "eth_clk_rx_clk",
582				       "eth_rx_dv",
583				       "eth_rxd0",
584				       "eth_rxd1",
585				       "eth_tx_en",
586				       "eth_txd0",
587				       "eth_txd1";
588				function = "eth";
589			};
590		};
591
592		pwm_a_x_pins: pwm_a_x {
593			mux {
594				groups = "pwm_a_x";
595				function = "pwm_a_x";
596			};
597		};
598
599		pwm_a_y_pins: pwm_a_y {
600			mux {
601				groups = "pwm_a_y";
602				function = "pwm_a_y";
603			};
604		};
605
606		pwm_b_pins: pwm_b {
607			mux {
608				groups = "pwm_b";
609				function = "pwm_b";
610			};
611		};
612
613		pwm_d_pins: pwm_d {
614			mux {
615				groups = "pwm_d";
616				function = "pwm_d";
617			};
618		};
619
620		pwm_e_pins: pwm_e {
621			mux {
622				groups = "pwm_e";
623				function = "pwm_e";
624			};
625		};
626
627		pwm_f_x_pins: pwm_f_x {
628			mux {
629				groups = "pwm_f_x";
630				function = "pwm_f_x";
631			};
632		};
633
634		pwm_f_y_pins: pwm_f_y {
635			mux {
636				groups = "pwm_f_y";
637				function = "pwm_f_y";
638			};
639		};
640
641		hdmi_hpd_pins: hdmi_hpd {
642			mux {
643				groups = "hdmi_hpd";
644				function = "hdmi_hpd";
645			};
646		};
647
648		hdmi_i2c_pins: hdmi_i2c {
649			mux {
650				groups = "hdmi_sda", "hdmi_scl";
651				function = "hdmi_i2c";
652			};
653		};
654
655		i2sout_ch23_y_pins: i2sout_ch23_y {
656			mux {
657				groups = "i2sout_ch23_y";
658				function = "i2s_out";
659			};
660		};
661
662		i2sout_ch45_y_pins: i2sout_ch45_y {
663			mux {
664				groups = "i2sout_ch45_y";
665				function = "i2s_out";
666			};
667		};
668
669		i2sout_ch67_y_pins: i2sout_ch67_y {
670			mux {
671				groups = "i2sout_ch67_y";
672				function = "i2s_out";
673			};
674		};
675
676		spdif_out_y_pins: spdif_out_y {
677			mux {
678				groups = "spdif_out_y";
679				function = "spdif_out";
680			};
681		};
682	};
683};
684
685&saradc {
686	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
687	clocks = <&xtal>,
688		 <&clkc CLKID_SAR_ADC>,
689		 <&clkc CLKID_SANA>,
690		 <&clkc CLKID_SAR_ADC_CLK>,
691		 <&clkc CLKID_SAR_ADC_SEL>;
692	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
693};
694
695&sd_emmc_a {
696	clocks = <&clkc CLKID_SD_EMMC_A>,
697		 <&clkc CLKID_SD_EMMC_A_CLK0>,
698		 <&clkc CLKID_FCLK_DIV2>;
699	clock-names = "core", "clkin0", "clkin1";
700};
701
702&sd_emmc_b {
703	clocks = <&clkc CLKID_SD_EMMC_B>,
704		 <&clkc CLKID_SD_EMMC_B_CLK0>,
705		 <&clkc CLKID_FCLK_DIV2>;
706	clock-names = "core", "clkin0", "clkin1";
707};
708
709&sd_emmc_c {
710	clocks = <&clkc CLKID_SD_EMMC_C>,
711		 <&clkc CLKID_SD_EMMC_C_CLK0>,
712		 <&clkc CLKID_FCLK_DIV2>;
713	clock-names = "core", "clkin0", "clkin1";
714};
715
716&spicc {
717	clocks = <&clkc CLKID_SPICC>;
718	clock-names = "core";
719	resets = <&reset RESET_PERIPHS_SPICC>;
720	num-cs = <1>;
721};
722
723&spifc {
724	clocks = <&clkc CLKID_SPI>;
725};
726
727&uart_A {
728	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
729	clock-names = "xtal", "pclk", "baud";
730};
731
732&uart_AO {
733	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
734	clock-names = "xtal", "pclk", "baud";
735};
736
737&uart_AO_B {
738	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
739	clock-names = "xtal", "pclk", "baud";
740};
741
742&uart_B {
743	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
744	clock-names = "xtal", "core", "baud";
745};
746
747&uart_C {
748	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
749	clock-names = "xtal", "core", "baud";
750};
751
752&vpu {
753	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
754};
755