1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 4 * 5 * 6 * Name: mpi2.h 7 * Title: MPI Message independent structures and definitions 8 * including System Interface Register Set and 9 * scatter/gather formats. 10 * Creation Date: June 21, 2006 11 * 12 * mpi2.h Version: 02.00.42 13 * 14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 15 * prefix are for use only on MPI v2.5 products, and must not be used 16 * with MPI v2.0 products. Unless otherwise noted, names beginning with 17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 18 * 19 * Version History 20 * --------------- 21 * 22 * Date Version Description 23 * -------- -------- ------------------------------------------------------ 24 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 25 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 26 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 27 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Moved ReplyPostHostIndex register to offset 0x6C of the 29 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 30 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 31 * Added union of request descriptors. 32 * Added union of reply descriptors. 33 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 34 * Added define for MPI2_VERSION_02_00. 35 * Fixed the size of the FunctionDependent5 field in the 36 * MPI2_DEFAULT_REPLY structure. 37 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 38 * Removed the MPI-defined Fault Codes and extended the 39 * product specific codes up to 0xEFFF. 40 * Added a sixth key value for the WriteSequence register 41 * and changed the flush value to 0x0. 42 * Added message function codes for Diagnostic Buffer Post 43 * and Diagnsotic Release. 44 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 45 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 46 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 47 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 49 * Added #defines for marking a reply descriptor as unused. 50 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 51 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 52 * Moved LUN field defines from mpi2_init.h. 53 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 54 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 55 * In all request and reply descriptors, replaced VF_ID 56 * field with MSIxIndex field. 57 * Removed DevHandle field from 58 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 59 * bytes reserved. 60 * Added RAID Accelerator functionality. 61 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 62 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Added MSI-x index mask and shift for Reply Post Host 64 * Index register. 65 * Added function code for Host Based Discovery Action. 66 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 67 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 68 * Added defines for product-specific range of message 69 * function codes, 0xF0 to 0xFF. 70 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 71 * Added alternative defines for the SGE Direction bit. 72 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 74 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 75 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 76 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 77 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 81 * Incorporating additions for MPI v2.5. 82 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 84 * Added Hard Reset delay timings. 85 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 87 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 88 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 89 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 90 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 91 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 92 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 94 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT 95 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 96 * 11-18-14 02.00.36 Updated copyright information. 97 * Bumped MPI2_HEADER_VERSION_UNIT. 98 * 03-16-15 02.00.37 Bumped MPI2_HEADER_VERSION_UNIT. 99 * Added Scratchpad registers to 100 * MPI2_SYSTEM_INTERFACE_REGS. 101 * Added MPI2_DIAG_SBR_RELOAD. 102 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 103 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT. 104 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 105 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 106 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 107 * -------------------------------------------------------------------------- 108 */ 109 110 #ifndef MPI2_H 111 #define MPI2_H 112 113 /***************************************************************************** 114 * 115 * MPI Version Definitions 116 * 117 *****************************************************************************/ 118 119 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 120 #define MPI2_VERSION_MAJOR_SHIFT (8) 121 #define MPI2_VERSION_MINOR_MASK (0x00FF) 122 #define MPI2_VERSION_MINOR_SHIFT (0) 123 124 /*major version for all MPI v2.x */ 125 #define MPI2_VERSION_MAJOR (0x02) 126 127 /*minor version for MPI v2.0 compatible products */ 128 #define MPI2_VERSION_MINOR (0x00) 129 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 130 MPI2_VERSION_MINOR) 131 #define MPI2_VERSION_02_00 (0x0200) 132 133 /*minor version for MPI v2.5 compatible products */ 134 #define MPI25_VERSION_MINOR (0x05) 135 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 136 MPI25_VERSION_MINOR) 137 #define MPI2_VERSION_02_05 (0x0205) 138 139 /*minor version for MPI v2.6 compatible products */ 140 #define MPI26_VERSION_MINOR (0x06) 141 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 142 MPI26_VERSION_MINOR) 143 #define MPI2_VERSION_02_06 (0x0206) 144 145 /*Unit and Dev versioning for this MPI header set */ 146 #define MPI2_HEADER_VERSION_UNIT (0x2A) 147 #define MPI2_HEADER_VERSION_DEV (0x00) 148 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 149 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 150 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 151 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 152 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 153 MPI2_HEADER_VERSION_DEV) 154 155 /***************************************************************************** 156 * 157 * IOC State Definitions 158 * 159 *****************************************************************************/ 160 161 #define MPI2_IOC_STATE_RESET (0x00000000) 162 #define MPI2_IOC_STATE_READY (0x10000000) 163 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 164 #define MPI2_IOC_STATE_FAULT (0x40000000) 165 166 #define MPI2_IOC_STATE_MASK (0xF0000000) 167 #define MPI2_IOC_STATE_SHIFT (28) 168 169 /*Fault state range for prodcut specific codes */ 170 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 171 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 172 173 /***************************************************************************** 174 * 175 * System Interface Register Definitions 176 * 177 *****************************************************************************/ 178 179 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS { 180 U32 Doorbell; /*0x00 */ 181 U32 WriteSequence; /*0x04 */ 182 U32 HostDiagnostic; /*0x08 */ 183 U32 Reserved1; /*0x0C */ 184 U32 DiagRWData; /*0x10 */ 185 U32 DiagRWAddressLow; /*0x14 */ 186 U32 DiagRWAddressHigh; /*0x18 */ 187 U32 Reserved2[5]; /*0x1C */ 188 U32 HostInterruptStatus; /*0x30 */ 189 U32 HostInterruptMask; /*0x34 */ 190 U32 DCRData; /*0x38 */ 191 U32 DCRAddress; /*0x3C */ 192 U32 Reserved3[2]; /*0x40 */ 193 U32 ReplyFreeHostIndex; /*0x48 */ 194 U32 Reserved4[8]; /*0x4C */ 195 U32 ReplyPostHostIndex; /*0x6C */ 196 U32 Reserved5; /*0x70 */ 197 U32 HCBSize; /*0x74 */ 198 U32 HCBAddressLow; /*0x78 */ 199 U32 HCBAddressHigh; /*0x7C */ 200 U32 Reserved6[12]; /*0x80 */ 201 U32 Scratchpad[4]; /*0xB0 */ 202 U32 RequestDescriptorPostLow; /*0xC0 */ 203 U32 RequestDescriptorPostHigh; /*0xC4 */ 204 U32 AtomicRequestDescriptorPost;/*0xC8 */ 205 U32 Reserved7[13]; /*0xCC */ 206 } MPI2_SYSTEM_INTERFACE_REGS, 207 *PTR_MPI2_SYSTEM_INTERFACE_REGS, 208 Mpi2SystemInterfaceRegs_t, 209 *pMpi2SystemInterfaceRegs_t; 210 211 /* 212 *Defines for working with the Doorbell register. 213 */ 214 #define MPI2_DOORBELL_OFFSET (0x00000000) 215 216 /*IOC --> System values */ 217 #define MPI2_DOORBELL_USED (0x08000000) 218 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 219 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 220 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 221 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 222 223 /*System --> IOC values */ 224 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 225 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 226 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 227 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 228 229 /* 230 *Defines for the WriteSequence register 231 */ 232 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 233 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 234 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 235 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 236 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 237 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 238 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 239 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 240 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 241 242 /* 243 *Defines for the HostDiagnostic register 244 */ 245 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 246 247 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 248 249 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 250 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 251 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 252 253 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 254 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 255 #define MPI2_DIAG_HCB_MODE (0x00000100) 256 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 257 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 258 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 259 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 260 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 261 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 262 263 /* 264 *Offsets for DiagRWData and address 265 */ 266 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 267 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 268 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 269 270 /* 271 *Defines for the HostInterruptStatus register 272 */ 273 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 274 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 275 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 276 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 277 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 278 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 279 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 280 281 /* 282 *Defines for the HostInterruptMask register 283 */ 284 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 285 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 286 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 287 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 288 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 289 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 290 291 /* 292 *Offsets for DCRData and address 293 */ 294 #define MPI2_DCR_DATA_OFFSET (0x00000038) 295 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 296 297 /* 298 *Offset for the Reply Free Queue 299 */ 300 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 301 302 /* 303 *Defines for the Reply Descriptor Post Queue 304 */ 305 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 306 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 307 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 308 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 309 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/ 310 311 312 /* 313 *Defines for the HCBSize and address 314 */ 315 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 316 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 317 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 318 319 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 320 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 321 322 /* 323 *Offsets for the Scratchpad registers 324 */ 325 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 326 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 327 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 328 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 329 330 /* 331 *Offsets for the Request Descriptor Post Queue 332 */ 333 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 334 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 335 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 336 337 /*Hard Reset delay timings */ 338 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 339 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 340 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 341 342 /***************************************************************************** 343 * 344 * Message Descriptors 345 * 346 *****************************************************************************/ 347 348 /*Request Descriptors */ 349 350 /*Default Request Descriptor */ 351 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 352 U8 RequestFlags; /*0x00 */ 353 U8 MSIxIndex; /*0x01 */ 354 U16 SMID; /*0x02 */ 355 U16 LMID; /*0x04 */ 356 U16 DescriptorTypeDependent; /*0x06 */ 357 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 358 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 359 Mpi2DefaultRequestDescriptor_t, 360 *pMpi2DefaultRequestDescriptor_t; 361 362 /*defines for the RequestFlags field */ 363 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 364 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) 365 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 366 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 367 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 368 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 369 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 370 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 371 372 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 373 374 /*High Priority Request Descriptor */ 375 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 376 U8 RequestFlags; /*0x00 */ 377 U8 MSIxIndex; /*0x01 */ 378 U16 SMID; /*0x02 */ 379 U16 LMID; /*0x04 */ 380 U16 Reserved1; /*0x06 */ 381 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 382 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 383 Mpi2HighPriorityRequestDescriptor_t, 384 *pMpi2HighPriorityRequestDescriptor_t; 385 386 /*SCSI IO Request Descriptor */ 387 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 388 U8 RequestFlags; /*0x00 */ 389 U8 MSIxIndex; /*0x01 */ 390 U16 SMID; /*0x02 */ 391 U16 LMID; /*0x04 */ 392 U16 DevHandle; /*0x06 */ 393 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 394 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 395 Mpi2SCSIIORequestDescriptor_t, 396 *pMpi2SCSIIORequestDescriptor_t; 397 398 /*SCSI Target Request Descriptor */ 399 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 400 U8 RequestFlags; /*0x00 */ 401 U8 MSIxIndex; /*0x01 */ 402 U16 SMID; /*0x02 */ 403 U16 LMID; /*0x04 */ 404 U16 IoIndex; /*0x06 */ 405 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 406 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 407 Mpi2SCSITargetRequestDescriptor_t, 408 *pMpi2SCSITargetRequestDescriptor_t; 409 410 /*RAID Accelerator Request Descriptor */ 411 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 412 U8 RequestFlags; /*0x00 */ 413 U8 MSIxIndex; /*0x01 */ 414 U16 SMID; /*0x02 */ 415 U16 LMID; /*0x04 */ 416 U16 Reserved; /*0x06 */ 417 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 418 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 419 Mpi2RAIDAcceleratorRequestDescriptor_t, 420 *pMpi2RAIDAcceleratorRequestDescriptor_t; 421 422 /*Fast Path SCSI IO Request Descriptor */ 423 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 424 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 425 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 426 Mpi25FastPathSCSIIORequestDescriptor_t, 427 *pMpi25FastPathSCSIIORequestDescriptor_t; 428 429 /*union of Request Descriptors */ 430 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { 431 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 432 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 433 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 434 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 435 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 436 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 437 U64 Words; 438 } MPI2_REQUEST_DESCRIPTOR_UNION, 439 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 440 Mpi2RequestDescriptorUnion_t, 441 *pMpi2RequestDescriptorUnion_t; 442 443 /*Atomic Request Descriptors */ 444 445 /* 446 * All Atomic Request Descriptors have the same format, so the following 447 * structure is used for all Atomic Request Descriptors: 448 * Atomic Default Request Descriptor 449 * Atomic High Priority Request Descriptor 450 * Atomic SCSI IO Request Descriptor 451 * Atomic SCSI Target Request Descriptor 452 * Atomic RAID Accelerator Request Descriptor 453 * Atomic Fast Path SCSI IO Request Descriptor 454 */ 455 456 /*Atomic Request Descriptor */ 457 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR { 458 U8 RequestFlags; /* 0x00 */ 459 U8 MSIxIndex; /* 0x01 */ 460 U16 SMID; /* 0x02 */ 461 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 462 *PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 463 Mpi26AtomicRequestDescriptor_t, 464 *pMpi26AtomicRequestDescriptor_t; 465 466 /*for the RequestFlags field, use the same 467 *defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR 468 */ 469 470 /*Reply Descriptors */ 471 472 /*Default Reply Descriptor */ 473 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 474 U8 ReplyFlags; /*0x00 */ 475 U8 MSIxIndex; /*0x01 */ 476 U16 DescriptorTypeDependent1; /*0x02 */ 477 U32 DescriptorTypeDependent2; /*0x04 */ 478 } MPI2_DEFAULT_REPLY_DESCRIPTOR, 479 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 480 Mpi2DefaultReplyDescriptor_t, 481 *pMpi2DefaultReplyDescriptor_t; 482 483 /*defines for the ReplyFlags field */ 484 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 485 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 486 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 487 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 488 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 489 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 490 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 491 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 492 493 /*values for marking a reply descriptor as unused */ 494 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 495 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 496 497 /*Address Reply Descriptor */ 498 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 499 U8 ReplyFlags; /*0x00 */ 500 U8 MSIxIndex; /*0x01 */ 501 U16 SMID; /*0x02 */ 502 U32 ReplyFrameAddress; /*0x04 */ 503 } MPI2_ADDRESS_REPLY_DESCRIPTOR, 504 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 505 Mpi2AddressReplyDescriptor_t, 506 *pMpi2AddressReplyDescriptor_t; 507 508 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 509 510 /*SCSI IO Success Reply Descriptor */ 511 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 512 U8 ReplyFlags; /*0x00 */ 513 U8 MSIxIndex; /*0x01 */ 514 U16 SMID; /*0x02 */ 515 U16 TaskTag; /*0x04 */ 516 U16 Reserved1; /*0x06 */ 517 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 518 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 519 Mpi2SCSIIOSuccessReplyDescriptor_t, 520 *pMpi2SCSIIOSuccessReplyDescriptor_t; 521 522 /*TargetAssist Success Reply Descriptor */ 523 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 524 U8 ReplyFlags; /*0x00 */ 525 U8 MSIxIndex; /*0x01 */ 526 U16 SMID; /*0x02 */ 527 U8 SequenceNumber; /*0x04 */ 528 U8 Reserved1; /*0x05 */ 529 U16 IoIndex; /*0x06 */ 530 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 531 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 532 Mpi2TargetAssistSuccessReplyDescriptor_t, 533 *pMpi2TargetAssistSuccessReplyDescriptor_t; 534 535 /*Target Command Buffer Reply Descriptor */ 536 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 537 U8 ReplyFlags; /*0x00 */ 538 U8 MSIxIndex; /*0x01 */ 539 U8 VP_ID; /*0x02 */ 540 U8 Flags; /*0x03 */ 541 U16 InitiatorDevHandle; /*0x04 */ 542 U16 IoIndex; /*0x06 */ 543 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 544 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 545 Mpi2TargetCommandBufferReplyDescriptor_t, 546 *pMpi2TargetCommandBufferReplyDescriptor_t; 547 548 /*defines for Flags field */ 549 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 550 551 /*RAID Accelerator Success Reply Descriptor */ 552 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 553 U8 ReplyFlags; /*0x00 */ 554 U8 MSIxIndex; /*0x01 */ 555 U16 SMID; /*0x02 */ 556 U32 Reserved; /*0x04 */ 557 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 558 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 559 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 560 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 561 562 /*Fast Path SCSI IO Success Reply Descriptor */ 563 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 564 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 565 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 566 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 567 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 568 569 /*union of Reply Descriptors */ 570 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 571 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 572 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 573 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 574 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 575 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 576 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 577 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 578 U64 Words; 579 } MPI2_REPLY_DESCRIPTORS_UNION, 580 *PTR_MPI2_REPLY_DESCRIPTORS_UNION, 581 Mpi2ReplyDescriptorsUnion_t, 582 *pMpi2ReplyDescriptorsUnion_t; 583 584 /***************************************************************************** 585 * 586 * Message Functions 587 * 588 *****************************************************************************/ 589 590 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) 591 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 592 #define MPI2_FUNCTION_IOC_INIT (0x02) 593 #define MPI2_FUNCTION_IOC_FACTS (0x03) 594 #define MPI2_FUNCTION_CONFIG (0x04) 595 #define MPI2_FUNCTION_PORT_FACTS (0x05) 596 #define MPI2_FUNCTION_PORT_ENABLE (0x06) 597 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) 598 #define MPI2_FUNCTION_EVENT_ACK (0x08) 599 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) 600 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) 601 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) 602 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) 603 #define MPI2_FUNCTION_FW_UPLOAD (0x12) 604 #define MPI2_FUNCTION_RAID_ACTION (0x15) 605 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) 606 #define MPI2_FUNCTION_TOOLBOX (0x17) 607 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) 608 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) 609 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) 610 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) 611 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) 612 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) 613 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) 614 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) 615 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) 616 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) 617 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 618 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 619 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 620 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 621 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 622 623 /*Doorbell functions */ 624 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 625 #define MPI2_FUNCTION_HANDSHAKE (0x42) 626 627 /***************************************************************************** 628 * 629 * IOC Status Values 630 * 631 *****************************************************************************/ 632 633 /*mask for IOCStatus status value */ 634 #define MPI2_IOCSTATUS_MASK (0x7FFF) 635 636 /**************************************************************************** 637 * Common IOCStatus values for all replies 638 ****************************************************************************/ 639 640 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 641 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 642 #define MPI2_IOCSTATUS_BUSY (0x0002) 643 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 644 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 645 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 646 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 647 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 648 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 649 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 650 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 651 652 /**************************************************************************** 653 * Config IOCStatus values 654 ****************************************************************************/ 655 656 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 657 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 658 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 659 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 660 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 661 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 662 663 /**************************************************************************** 664 * SCSI IO Reply 665 ****************************************************************************/ 666 667 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 668 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 669 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 670 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 671 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 672 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 673 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 674 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 675 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 676 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 677 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 678 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 679 680 /**************************************************************************** 681 * For use by SCSI Initiator and SCSI Target end-to-end data protection 682 ****************************************************************************/ 683 684 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 685 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 686 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 687 688 /**************************************************************************** 689 * SCSI Target values 690 ****************************************************************************/ 691 692 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 693 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 694 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 695 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 696 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 697 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 698 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 699 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 700 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 701 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 702 703 /**************************************************************************** 704 * Serial Attached SCSI values 705 ****************************************************************************/ 706 707 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 708 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 709 710 /**************************************************************************** 711 * Diagnostic Buffer Post / Diagnostic Release values 712 ****************************************************************************/ 713 714 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 715 716 /**************************************************************************** 717 * RAID Accelerator values 718 ****************************************************************************/ 719 720 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 721 722 /**************************************************************************** 723 * IOCStatus flag to indicate that log info is available 724 ****************************************************************************/ 725 726 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 727 728 /**************************************************************************** 729 * IOCLogInfo Types 730 ****************************************************************************/ 731 732 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 733 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 734 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 735 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 736 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 737 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 738 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 739 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 740 741 /***************************************************************************** 742 * 743 * Standard Message Structures 744 * 745 *****************************************************************************/ 746 747 /**************************************************************************** 748 *Request Message Header for all request messages 749 ****************************************************************************/ 750 751 typedef struct _MPI2_REQUEST_HEADER { 752 U16 FunctionDependent1; /*0x00 */ 753 U8 ChainOffset; /*0x02 */ 754 U8 Function; /*0x03 */ 755 U16 FunctionDependent2; /*0x04 */ 756 U8 FunctionDependent3; /*0x06 */ 757 U8 MsgFlags; /*0x07 */ 758 U8 VP_ID; /*0x08 */ 759 U8 VF_ID; /*0x09 */ 760 U16 Reserved1; /*0x0A */ 761 } MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER, 762 MPI2RequestHeader_t, *pMPI2RequestHeader_t; 763 764 /**************************************************************************** 765 * Default Reply 766 ****************************************************************************/ 767 768 typedef struct _MPI2_DEFAULT_REPLY { 769 U16 FunctionDependent1; /*0x00 */ 770 U8 MsgLength; /*0x02 */ 771 U8 Function; /*0x03 */ 772 U16 FunctionDependent2; /*0x04 */ 773 U8 FunctionDependent3; /*0x06 */ 774 U8 MsgFlags; /*0x07 */ 775 U8 VP_ID; /*0x08 */ 776 U8 VF_ID; /*0x09 */ 777 U16 Reserved1; /*0x0A */ 778 U16 FunctionDependent5; /*0x0C */ 779 U16 IOCStatus; /*0x0E */ 780 U32 IOCLogInfo; /*0x10 */ 781 } MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY, 782 MPI2DefaultReply_t, *pMPI2DefaultReply_t; 783 784 /*common version structure/union used in messages and configuration pages */ 785 786 typedef struct _MPI2_VERSION_STRUCT { 787 U8 Dev; /*0x00 */ 788 U8 Unit; /*0x01 */ 789 U8 Minor; /*0x02 */ 790 U8 Major; /*0x03 */ 791 } MPI2_VERSION_STRUCT; 792 793 typedef union _MPI2_VERSION_UNION { 794 MPI2_VERSION_STRUCT Struct; 795 U32 Word; 796 } MPI2_VERSION_UNION; 797 798 /*LUN field defines, common to many structures */ 799 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 800 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 801 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 802 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 803 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 804 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 805 806 /***************************************************************************** 807 * 808 * Fusion-MPT MPI Scatter Gather Elements 809 * 810 *****************************************************************************/ 811 812 /**************************************************************************** 813 * MPI Simple Element structures 814 ****************************************************************************/ 815 816 typedef struct _MPI2_SGE_SIMPLE32 { 817 U32 FlagsLength; 818 U32 Address; 819 } MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32, 820 Mpi2SGESimple32_t, *pMpi2SGESimple32_t; 821 822 typedef struct _MPI2_SGE_SIMPLE64 { 823 U32 FlagsLength; 824 U64 Address; 825 } MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64, 826 Mpi2SGESimple64_t, *pMpi2SGESimple64_t; 827 828 typedef struct _MPI2_SGE_SIMPLE_UNION { 829 U32 FlagsLength; 830 union { 831 U32 Address32; 832 U64 Address64; 833 } u; 834 } MPI2_SGE_SIMPLE_UNION, 835 *PTR_MPI2_SGE_SIMPLE_UNION, 836 Mpi2SGESimpleUnion_t, 837 *pMpi2SGESimpleUnion_t; 838 839 /**************************************************************************** 840 * MPI Chain Element structures - for MPI v2.0 products only 841 ****************************************************************************/ 842 843 typedef struct _MPI2_SGE_CHAIN32 { 844 U16 Length; 845 U8 NextChainOffset; 846 U8 Flags; 847 U32 Address; 848 } MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32, 849 Mpi2SGEChain32_t, *pMpi2SGEChain32_t; 850 851 typedef struct _MPI2_SGE_CHAIN64 { 852 U16 Length; 853 U8 NextChainOffset; 854 U8 Flags; 855 U64 Address; 856 } MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64, 857 Mpi2SGEChain64_t, *pMpi2SGEChain64_t; 858 859 typedef struct _MPI2_SGE_CHAIN_UNION { 860 U16 Length; 861 U8 NextChainOffset; 862 U8 Flags; 863 union { 864 U32 Address32; 865 U64 Address64; 866 } u; 867 } MPI2_SGE_CHAIN_UNION, 868 *PTR_MPI2_SGE_CHAIN_UNION, 869 Mpi2SGEChainUnion_t, 870 *pMpi2SGEChainUnion_t; 871 872 /**************************************************************************** 873 * MPI Transaction Context Element structures - for MPI v2.0 products only 874 ****************************************************************************/ 875 876 typedef struct _MPI2_SGE_TRANSACTION32 { 877 U8 Reserved; 878 U8 ContextSize; 879 U8 DetailsLength; 880 U8 Flags; 881 U32 TransactionContext[1]; 882 U32 TransactionDetails[1]; 883 } MPI2_SGE_TRANSACTION32, 884 *PTR_MPI2_SGE_TRANSACTION32, 885 Mpi2SGETransaction32_t, 886 *pMpi2SGETransaction32_t; 887 888 typedef struct _MPI2_SGE_TRANSACTION64 { 889 U8 Reserved; 890 U8 ContextSize; 891 U8 DetailsLength; 892 U8 Flags; 893 U32 TransactionContext[2]; 894 U32 TransactionDetails[1]; 895 } MPI2_SGE_TRANSACTION64, 896 *PTR_MPI2_SGE_TRANSACTION64, 897 Mpi2SGETransaction64_t, 898 *pMpi2SGETransaction64_t; 899 900 typedef struct _MPI2_SGE_TRANSACTION96 { 901 U8 Reserved; 902 U8 ContextSize; 903 U8 DetailsLength; 904 U8 Flags; 905 U32 TransactionContext[3]; 906 U32 TransactionDetails[1]; 907 } MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96, 908 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t; 909 910 typedef struct _MPI2_SGE_TRANSACTION128 { 911 U8 Reserved; 912 U8 ContextSize; 913 U8 DetailsLength; 914 U8 Flags; 915 U32 TransactionContext[4]; 916 U32 TransactionDetails[1]; 917 } MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128, 918 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128; 919 920 typedef struct _MPI2_SGE_TRANSACTION_UNION { 921 U8 Reserved; 922 U8 ContextSize; 923 U8 DetailsLength; 924 U8 Flags; 925 union { 926 U32 TransactionContext32[1]; 927 U32 TransactionContext64[2]; 928 U32 TransactionContext96[3]; 929 U32 TransactionContext128[4]; 930 } u; 931 U32 TransactionDetails[1]; 932 } MPI2_SGE_TRANSACTION_UNION, 933 *PTR_MPI2_SGE_TRANSACTION_UNION, 934 Mpi2SGETransactionUnion_t, 935 *pMpi2SGETransactionUnion_t; 936 937 /**************************************************************************** 938 * MPI SGE union for IO SGL's - for MPI v2.0 products only 939 ****************************************************************************/ 940 941 typedef struct _MPI2_MPI_SGE_IO_UNION { 942 union { 943 MPI2_SGE_SIMPLE_UNION Simple; 944 MPI2_SGE_CHAIN_UNION Chain; 945 } u; 946 } MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION, 947 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t; 948 949 /**************************************************************************** 950 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 951 ****************************************************************************/ 952 953 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION { 954 union { 955 MPI2_SGE_SIMPLE_UNION Simple; 956 MPI2_SGE_TRANSACTION_UNION Transaction; 957 } u; 958 } MPI2_SGE_TRANS_SIMPLE_UNION, 959 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 960 Mpi2SGETransSimpleUnion_t, 961 *pMpi2SGETransSimpleUnion_t; 962 963 /**************************************************************************** 964 * All MPI SGE types union 965 ****************************************************************************/ 966 967 typedef struct _MPI2_MPI_SGE_UNION { 968 union { 969 MPI2_SGE_SIMPLE_UNION Simple; 970 MPI2_SGE_CHAIN_UNION Chain; 971 MPI2_SGE_TRANSACTION_UNION Transaction; 972 } u; 973 } MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION, 974 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t; 975 976 /**************************************************************************** 977 * MPI SGE field definition and masks 978 ****************************************************************************/ 979 980 /*Flags field bit definitions */ 981 982 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 983 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 984 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 985 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 986 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 987 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 988 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 989 990 #define MPI2_SGE_FLAGS_SHIFT (24) 991 992 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 993 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 994 995 /*Element Type */ 996 997 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 998 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 999 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 1000 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1001 1002 /*Address location */ 1003 1004 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1005 1006 /*Direction */ 1007 1008 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1009 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1010 1011 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1012 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1013 1014 /*Address Size */ 1015 1016 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1017 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1018 1019 /*Context Size */ 1020 1021 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1022 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1023 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1024 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1025 1026 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1027 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1028 1029 /**************************************************************************** 1030 * MPI SGE operation Macros 1031 ****************************************************************************/ 1032 1033 /*SIMPLE FlagsLength manipulations... */ 1034 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1035 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \ 1036 MPI2_SGE_FLAGS_SHIFT) 1037 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1038 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1039 1040 #define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \ 1041 MPI2_SGE_LENGTH(l)) 1042 1043 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1044 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1045 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1046 MPI2_SGE_SET_FLAGS_LENGTH(f, l)) 1047 1048 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1049 #define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1050 MPI2_SGE_SET_FLAGS(f)) 1051 #define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1052 MPI2_SGE_LENGTH(l)) 1053 1054 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \ 1055 MPI2_SGE_CHAIN_OFFSET_SHIFT) 1056 1057 /***************************************************************************** 1058 * 1059 * Fusion-MPT IEEE Scatter Gather Elements 1060 * 1061 *****************************************************************************/ 1062 1063 /**************************************************************************** 1064 * IEEE Simple Element structures 1065 ****************************************************************************/ 1066 1067 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1068 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 1069 U32 Address; 1070 U32 FlagsLength; 1071 } MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32, 1072 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t; 1073 1074 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 1075 U64 Address; 1076 U32 Length; 1077 U16 Reserved1; 1078 U8 Reserved2; 1079 U8 Flags; 1080 } MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64, 1081 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t; 1082 1083 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 1084 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1085 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1086 } MPI2_IEEE_SGE_SIMPLE_UNION, 1087 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1088 Mpi2IeeeSgeSimpleUnion_t, 1089 *pMpi2IeeeSgeSimpleUnion_t; 1090 1091 /**************************************************************************** 1092 * IEEE Chain Element structures 1093 ****************************************************************************/ 1094 1095 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1096 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1097 1098 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1099 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1100 1101 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 1102 MPI2_IEEE_SGE_CHAIN32 Chain32; 1103 MPI2_IEEE_SGE_CHAIN64 Chain64; 1104 } MPI2_IEEE_SGE_CHAIN_UNION, 1105 *PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1106 Mpi2IeeeSgeChainUnion_t, 1107 *pMpi2IeeeSgeChainUnion_t; 1108 1109 /*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1110 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 1111 U64 Address; 1112 U32 Length; 1113 U16 Reserved1; 1114 U8 NextChainOffset; 1115 U8 Flags; 1116 } MPI25_IEEE_SGE_CHAIN64, 1117 *PTR_MPI25_IEEE_SGE_CHAIN64, 1118 Mpi25IeeeSgeChain64_t, 1119 *pMpi25IeeeSgeChain64_t; 1120 1121 /**************************************************************************** 1122 * All IEEE SGE types union 1123 ****************************************************************************/ 1124 1125 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1126 typedef struct _MPI2_IEEE_SGE_UNION { 1127 union { 1128 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1129 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1130 } u; 1131 } MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION, 1132 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t; 1133 1134 /**************************************************************************** 1135 * IEEE SGE union for IO SGL's 1136 ****************************************************************************/ 1137 1138 typedef union _MPI25_SGE_IO_UNION { 1139 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1140 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1141 } MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION, 1142 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t; 1143 1144 /**************************************************************************** 1145 * IEEE SGE field definitions and masks 1146 ****************************************************************************/ 1147 1148 /*Flags field bit definitions */ 1149 1150 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1151 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1152 1153 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1154 1155 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1156 1157 /*Element Type */ 1158 1159 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1160 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1161 1162 /*Next Segment Format */ 1163 1164 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1165 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1166 1167 /*Data Location Address Space */ 1168 1169 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1170 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1171 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1172 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1173 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1174 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1175 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1176 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) 1177 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) 1178 1179 /**************************************************************************** 1180 * IEEE SGE operation Macros 1181 ****************************************************************************/ 1182 1183 /*SIMPLE FlagsLength manipulations... */ 1184 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1185 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \ 1186 >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1187 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1188 1189 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\ 1190 MPI2_IEEE32_SGE_LENGTH(l)) 1191 1192 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \ 1193 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1194 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \ 1195 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1196 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \ 1197 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l)) 1198 1199 /*CAUTION - The following are READ-MODIFY-WRITE! */ 1200 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \ 1201 MPI2_IEEE32_SGE_SET_FLAGS(f)) 1202 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \ 1203 MPI2_IEEE32_SGE_LENGTH(l)) 1204 1205 /***************************************************************************** 1206 * 1207 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1208 * 1209 *****************************************************************************/ 1210 1211 typedef union _MPI2_SIMPLE_SGE_UNION { 1212 MPI2_SGE_SIMPLE_UNION MpiSimple; 1213 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1214 } MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION, 1215 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t; 1216 1217 typedef union _MPI2_SGE_IO_UNION { 1218 MPI2_SGE_SIMPLE_UNION MpiSimple; 1219 MPI2_SGE_CHAIN_UNION MpiChain; 1220 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1221 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1222 } MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION, 1223 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t; 1224 1225 /**************************************************************************** 1226 * 1227 * Values for SGLFlags field, used in many request messages with an SGL 1228 * 1229 ****************************************************************************/ 1230 1231 /*values for MPI SGL Data Location Address Space subfield */ 1232 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1233 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1234 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1235 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1236 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1237 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1238 /*values for SGL Type subfield */ 1239 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1240 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1241 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1242 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1243 1244 #endif 1245