1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18
19 #define PA_BASE 0
20 #define PB_BASE 32
21 #define PC_BASE 64
22 #define PD_BASE 96
23 #define PE_BASE 128
24 #define PF_BASE 160
25 #define PG_BASE 192
26 #define PH_BASE 224
27 #define PI_BASE 256
28 #define PL_BASE 352
29 #define PM_BASE 384
30 #define PN_BASE 416
31
32 #define SUNXI_PINCTRL_PIN(bank, pin) \
33 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
34
35 #define SUNXI_PIN_NAME_MAX_LEN 5
36
37 #define BANK_MEM_SIZE 0x24
38 #define MUX_REGS_OFFSET 0x0
39 #define DATA_REGS_OFFSET 0x10
40 #define DLEVEL_REGS_OFFSET 0x14
41 #define PULL_REGS_OFFSET 0x1c
42
43 #define PINS_PER_BANK 32
44 #define MUX_PINS_PER_REG 8
45 #define MUX_PINS_BITS 4
46 #define MUX_PINS_MASK 0x0f
47 #define DATA_PINS_PER_REG 32
48 #define DATA_PINS_BITS 1
49 #define DATA_PINS_MASK 0x01
50 #define DLEVEL_PINS_PER_REG 16
51 #define DLEVEL_PINS_BITS 2
52 #define DLEVEL_PINS_MASK 0x03
53 #define PULL_PINS_PER_REG 16
54 #define PULL_PINS_BITS 2
55 #define PULL_PINS_MASK 0x03
56
57 #define IRQ_PER_BANK 32
58
59 #define IRQ_CFG_REG 0x200
60 #define IRQ_CFG_IRQ_PER_REG 8
61 #define IRQ_CFG_IRQ_BITS 4
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
63 #define IRQ_CTRL_REG 0x210
64 #define IRQ_CTRL_IRQ_PER_REG 32
65 #define IRQ_CTRL_IRQ_BITS 1
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
67 #define IRQ_STATUS_REG 0x214
68 #define IRQ_STATUS_IRQ_PER_REG 32
69 #define IRQ_STATUS_IRQ_BITS 1
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
71
72 #define IRQ_DEBOUNCE_REG 0x218
73
74 #define IRQ_MEM_SIZE 0x20
75
76 #define IRQ_EDGE_RISING 0x00
77 #define IRQ_EDGE_FALLING 0x01
78 #define IRQ_LEVEL_HIGH 0x02
79 #define IRQ_LEVEL_LOW 0x03
80 #define IRQ_EDGE_BOTH 0x04
81
82 #define SUN4I_FUNC_INPUT 0
83 #define SUN4I_FUNC_IRQ 6
84
85 #define PINCTRL_SUN5I_A10S BIT(1)
86 #define PINCTRL_SUN5I_A13 BIT(2)
87 #define PINCTRL_SUN5I_GR8 BIT(3)
88 #define PINCTRL_SUN6I_A31 BIT(4)
89 #define PINCTRL_SUN6I_A31S BIT(5)
90 #define PINCTRL_SUN4I_A10 BIT(6)
91 #define PINCTRL_SUN7I_A20 BIT(7)
92 #define PINCTRL_SUN8I_R40 BIT(8)
93
94 struct sunxi_desc_function {
95 unsigned long variant;
96 const char *name;
97 u8 muxval;
98 u8 irqbank;
99 u8 irqnum;
100 };
101
102 struct sunxi_desc_pin {
103 struct pinctrl_pin_desc pin;
104 unsigned long variant;
105 struct sunxi_desc_function *functions;
106 };
107
108 struct sunxi_pinctrl_desc {
109 const struct sunxi_desc_pin *pins;
110 int npins;
111 unsigned pin_base;
112 unsigned irq_banks;
113 unsigned irq_bank_base;
114 bool irq_read_needs_mux;
115 };
116
117 struct sunxi_pinctrl_function {
118 const char *name;
119 const char **groups;
120 unsigned ngroups;
121 };
122
123 struct sunxi_pinctrl_group {
124 const char *name;
125 unsigned pin;
126 };
127
128 struct sunxi_pinctrl {
129 void __iomem *membase;
130 struct gpio_chip *chip;
131 const struct sunxi_pinctrl_desc *desc;
132 struct device *dev;
133 struct irq_domain *domain;
134 struct sunxi_pinctrl_function *functions;
135 unsigned nfunctions;
136 struct sunxi_pinctrl_group *groups;
137 unsigned ngroups;
138 int *irq;
139 unsigned *irq_array;
140 raw_spinlock_t lock;
141 struct pinctrl_dev *pctl_dev;
142 unsigned long variant;
143 };
144
145 #define SUNXI_PIN(_pin, ...) \
146 { \
147 .pin = _pin, \
148 .functions = (struct sunxi_desc_function[]){ \
149 __VA_ARGS__, { } }, \
150 }
151
152 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
153 { \
154 .pin = _pin, \
155 .variant = _variant, \
156 .functions = (struct sunxi_desc_function[]){ \
157 __VA_ARGS__, { } }, \
158 }
159
160 #define SUNXI_FUNCTION(_val, _name) \
161 { \
162 .name = _name, \
163 .muxval = _val, \
164 }
165
166 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
167 { \
168 .name = _name, \
169 .muxval = _val, \
170 .variant = _variant, \
171 }
172
173 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
174 { \
175 .name = "irq", \
176 .muxval = _val, \
177 .irqnum = _irq, \
178 }
179
180 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
181 { \
182 .name = "irq", \
183 .muxval = _val, \
184 .irqbank = _bank, \
185 .irqnum = _irq, \
186 }
187
188 /*
189 * The sunXi PIO registers are organized as is:
190 * 0x00 - 0x0c Muxing values.
191 * 8 pins per register, each pin having a 4bits value
192 * 0x10 Pin values
193 * 32 bits per register, each pin corresponding to one bit
194 * 0x14 - 0x18 Drive level
195 * 16 pins per register, each pin having a 2bits value
196 * 0x1c - 0x20 Pull-Up values
197 * 16 pins per register, each pin having a 2bits value
198 *
199 * This is for the first bank. Each bank will have the same layout,
200 * with an offset being a multiple of 0x24.
201 *
202 * The following functions calculate from the pin number the register
203 * and the bit offset that we should access.
204 */
sunxi_mux_reg(u16 pin)205 static inline u32 sunxi_mux_reg(u16 pin)
206 {
207 u8 bank = pin / PINS_PER_BANK;
208 u32 offset = bank * BANK_MEM_SIZE;
209 offset += MUX_REGS_OFFSET;
210 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
211 return round_down(offset, 4);
212 }
213
sunxi_mux_offset(u16 pin)214 static inline u32 sunxi_mux_offset(u16 pin)
215 {
216 u32 pin_num = pin % MUX_PINS_PER_REG;
217 return pin_num * MUX_PINS_BITS;
218 }
219
sunxi_data_reg(u16 pin)220 static inline u32 sunxi_data_reg(u16 pin)
221 {
222 u8 bank = pin / PINS_PER_BANK;
223 u32 offset = bank * BANK_MEM_SIZE;
224 offset += DATA_REGS_OFFSET;
225 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
226 return round_down(offset, 4);
227 }
228
sunxi_data_offset(u16 pin)229 static inline u32 sunxi_data_offset(u16 pin)
230 {
231 u32 pin_num = pin % DATA_PINS_PER_REG;
232 return pin_num * DATA_PINS_BITS;
233 }
234
sunxi_dlevel_reg(u16 pin)235 static inline u32 sunxi_dlevel_reg(u16 pin)
236 {
237 u8 bank = pin / PINS_PER_BANK;
238 u32 offset = bank * BANK_MEM_SIZE;
239 offset += DLEVEL_REGS_OFFSET;
240 offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
241 return round_down(offset, 4);
242 }
243
sunxi_dlevel_offset(u16 pin)244 static inline u32 sunxi_dlevel_offset(u16 pin)
245 {
246 u32 pin_num = pin % DLEVEL_PINS_PER_REG;
247 return pin_num * DLEVEL_PINS_BITS;
248 }
249
sunxi_pull_reg(u16 pin)250 static inline u32 sunxi_pull_reg(u16 pin)
251 {
252 u8 bank = pin / PINS_PER_BANK;
253 u32 offset = bank * BANK_MEM_SIZE;
254 offset += PULL_REGS_OFFSET;
255 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
256 return round_down(offset, 4);
257 }
258
sunxi_pull_offset(u16 pin)259 static inline u32 sunxi_pull_offset(u16 pin)
260 {
261 u32 pin_num = pin % PULL_PINS_PER_REG;
262 return pin_num * PULL_PINS_BITS;
263 }
264
sunxi_irq_cfg_reg(u16 irq,unsigned bank_base)265 static inline u32 sunxi_irq_cfg_reg(u16 irq, unsigned bank_base)
266 {
267 u8 bank = irq / IRQ_PER_BANK;
268 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
269
270 return IRQ_CFG_REG + (bank_base + bank) * IRQ_MEM_SIZE + reg;
271 }
272
sunxi_irq_cfg_offset(u16 irq)273 static inline u32 sunxi_irq_cfg_offset(u16 irq)
274 {
275 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
276 return irq_num * IRQ_CFG_IRQ_BITS;
277 }
278
sunxi_irq_ctrl_reg_from_bank(u8 bank,unsigned bank_base)279 static inline u32 sunxi_irq_ctrl_reg_from_bank(u8 bank, unsigned bank_base)
280 {
281 return IRQ_CTRL_REG + (bank_base + bank) * IRQ_MEM_SIZE;
282 }
283
sunxi_irq_ctrl_reg(u16 irq,unsigned bank_base)284 static inline u32 sunxi_irq_ctrl_reg(u16 irq, unsigned bank_base)
285 {
286 u8 bank = irq / IRQ_PER_BANK;
287
288 return sunxi_irq_ctrl_reg_from_bank(bank, bank_base);
289 }
290
sunxi_irq_ctrl_offset(u16 irq)291 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
292 {
293 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
294 return irq_num * IRQ_CTRL_IRQ_BITS;
295 }
296
sunxi_irq_debounce_reg_from_bank(u8 bank,unsigned bank_base)297 static inline u32 sunxi_irq_debounce_reg_from_bank(u8 bank, unsigned bank_base)
298 {
299 return IRQ_DEBOUNCE_REG + (bank_base + bank) * IRQ_MEM_SIZE;
300 }
301
sunxi_irq_status_reg_from_bank(u8 bank,unsigned bank_base)302 static inline u32 sunxi_irq_status_reg_from_bank(u8 bank, unsigned bank_base)
303 {
304 return IRQ_STATUS_REG + (bank_base + bank) * IRQ_MEM_SIZE;
305 }
306
sunxi_irq_status_reg(u16 irq,unsigned bank_base)307 static inline u32 sunxi_irq_status_reg(u16 irq, unsigned bank_base)
308 {
309 u8 bank = irq / IRQ_PER_BANK;
310
311 return sunxi_irq_status_reg_from_bank(bank, bank_base);
312 }
313
sunxi_irq_status_offset(u16 irq)314 static inline u32 sunxi_irq_status_offset(u16 irq)
315 {
316 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
317 return irq_num * IRQ_STATUS_IRQ_BITS;
318 }
319
320 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
321 const struct sunxi_pinctrl_desc *desc,
322 unsigned long variant);
323
324 #define sunxi_pinctrl_init(_dev, _desc) \
325 sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
326
327 #endif /* __PINCTRL_SUNXI_H */
328