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/arch/metag/tbx/
Dtbictx.S23 #define A0_4 A0.4,
103 MOV A0.2,D1Ar3 /* Save pointer into A0.2 */
111 SETD [D1Ar1+#TBICTX_Ext_Ctx_pExt],A0.2
113 SETL [A0.2++],D0Ar6,D1Ar5 /* Save A0.2, A1.2 state */
120 MSETL [A0.2],D0.8,D0.9,D0.10,D0.11,D0.12,D0.13,D0.14,D0.15
123 SWAP D0Re0,A0.2 /* pDst into D0Re0 */
128 MSETL [D0Re0], A0_4 A0.5,A0.6,A0.7 /* Save 8*3 bytes */
131 SWAP D0Re0,A0.2 /* pDst back into A0.2 */
138 SETL [A0.2++],D0Ar6,D1Ar5 /* Save 8*1 bytes */
143 MSETL [A0.2],D0Ar6,D0FrT /* Save 8*2 bytes */
[all …]
Dtbisoft.S19 #define A0_4 ,A0.4
94 MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
105 ADD A0.2,D1Ar1,#TBICTX_DX+(8*5)
106 MGETL D0.5,D0.6,D0.7,[A0.2] /* Get caller-saved DX regs */
186 MOV A0.2,D1Ar1 /* A0.2 is new stack */
188 SETL [A0.2++],D0FrT,D1RtP /* Save return to __exit */
190 SETL [A0.2++],D0FrT,D1RtP /* Save return to fnMain */
192 MSETL [A0.2],D0Ar6,D0Ar4 /* Save extra initial args */
195 SETL [A0.2++],D0FrT,D1RtP /* Save return to ___TBIStart */
197 MOV D0Re0,A0.2 /* Return pCtx for new thread */
[all …]
Dtbipcx.S29 #define A0_4 ,A0.4
52 #define A0GblIStP A0.15 /* PTBICTX for current thread in PRIV system */
77 MOV A0.2,A0StP /* else push context here */
81 MOVMI A0.2,D1Ar1 /* use priv stack if PRIV set */
87 ADD A0.3,A0.2,#TBICTX_DX /* DX Save area */
91 SETL [A0.2],D0Ar6,D1Ar5 /* Push header fields */
92 ADD D0FrT,A0.2,#TBICTX_AX /* Address AX save area */
93 MSETL [A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
96 SETL [A0.3++],D0Ar6,D1Ar5 /* Zero CT register states */
97 SETL [A0.3++],D0Ar6,D1Ar5
[all …]
Dtbidspram.S32 MOV A0.3, D0Ar2
48 MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
66 MOV A0.3, D0Ar2
82 MSETL [A0.3++], D0Re0, D0Ar6, D0Ar4, D0.5
100 MOV A0.3, D0Ar2
112 MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
134 MOV A0.3, D0Ar2
146 MGETL D0Re0, D0Ar6, D0Ar4, D0.5, [A0.3++]
Dtbicore.S115 MOVT A0.3,#HI(LINSYSEVENT_WR_ATOMIC_LOCK)
118 SET [A0.3+#UON],D1RtP /* Stop shared memory access too */
119 DCACHE [D1Ar1],A0.3 /* Flush Cache line */
121 DCACHE [D1Ar1],A0.3 /* Flush Cache line */
126 SET [A0.3+#UOFF],D1RtP /* Allow shared memory access */
Dtbitimer.S70 SETLNZ [A0.3],D0Ar6,D1Ar5 /* ___TBITime(B/I)=-Start if enable */
123 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
155 SETL [A0.3],D0Ar4,D1Ar3 /* Update ___TBITime(B/I) */
186 GETD A0.3,[A1.3+#0] /* A0.3 == &___TBITimeB */
194 GETD A0.3,[A1.3+#4] /* A0.3 == &___TBITimeI */
201 GETL D0Ar4,D1Ar3,[A0.3] /* Read ___TBITime(B/I) */
/arch/c6x/lib/
Dcsum_64plus.S95 SHL .S1 A7,8,A0
98 || ADD .S1 A0,A9,A9
107 SHL .S1 A8,8,A0
110 || ADD .S1 A0,A9,A9
147 SHRU .S1 A9,16,A0
148 [A0] BNOP .S1 L91,5
209 L12: SHRU .S1 A5,16,A0
210 [!A0] BNOP .S1 L14,5
215 SHRU .S1 A5,16,A0
216 [A0] BNOP .S1 L13,5
[all …]
Dllshru.S26 mvk .s1 32,A0
27 sub .d1 A0,A1,A0
28 cmplt .l1 0,A0,A2
29 [A2] shl .s1 A5,A0,A0
31 [!A2] neg .l1 A0,A4
34 || [A2] or .d1 A4,A0,A4
Dllshl.S26 mvk .s1 32,A0
27 sub .d1 A0,A1,A0
28 cmplt .l1 0,A0,A2
29 [A2] shru .s1 A4,A0,A0
30 [!A2] neg .l1 A0,A5
33 || [A2] or .d1 A5,A0,A5
Dllshr.S26 mvk .s1 32,A0
27 sub .d1 A0,A1,A0
28 cmplt .l1 0,A0,A2
29 [A2] shl .s1 A5,A0,A0
31 [!A2] neg .l1 A0,A4
34 || [A2] or .d1 A4,A0,A4
Dnegll.S25 mvk .l1 0,A0
26 subu .l1 A0,A4,A3:A2
27 sub .l1 A0,A5,A0
29 add .l1 A5,A0,A5
Dmemcpy_64plus.S16 AND .L1 0x1,A6,A0
22 [A0] LDB .D2T1 *B4++,A5
29 [A0] STB .D1T1 A5,*A3++
Dstrasgi.S25 ldw .d2t1 *B4++, A0
35 || mv .s2x A0, B5
40 || [B0] ldw .d2t1 *B4++, A0
70 || mv .s2x A0, B5
Ddivi.S22 ;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
23 ;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
29 ;; A0 is not clobbered by any of the functions.
/arch/blackfin/lib/
Dmuldi3.S51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */ define
52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
53 A0 += A1; /* E1 */
54 R4 = A0.w;
55 A0 = R0.l * R3.l (FU); /* E2 */ define
56 A0 += R2.l * R1.l (FU); /* E2 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
65 A0 += A1; /* E2c */
66 R1 = A0.w;
/arch/metag/lib/
Dmemset.S16 ADD A0.2,D0Ar2,D0Re0 ! Duplicate byte value into 4 (A0.2)
34 MOV A1.2,A0.2
39 SETL [D1Ar1++],A0.2,A1.2
40 SETL [D1Ar1++],A0.2,A1.2
41 SETL [D1Ar1++],A0.2,A1.2
42 SETL [D1Ar1++],A0.2,A1.2
56 SETL [D1Ar1++],A0.2,A1.2
73 SETB [D1Ar1+#(-7)],A0.2
74 SETB [D1Ar1+#(-6)],A0.2
75 SETB [D1Ar1+#(-5)],A0.2
[all …]
Dmemmove.S30 MOV A0.2, D1Ar1
48 SETL [--A0.2], D0Re0, D1Re0
56 SETB [--A0.2], D1Re0
60 MOV D0Re0, A0.2
62 SUB A0.2, A0StP, #24
63 MGETL D0.5, D0.6, D0.7, [A0.2]
70 SETB [--A0.2], D0Re0
88 ! A0.2 dst 64-bit is aligned
131 SETL [--A0.2], D0Re0, D1Re0
168 SETL [--A0.2], D0Re0, D1Re0
[all …]
Ddiv64.S13 ORS A0.3,D1Ar3,D0Ar4
42 ORS A0.3,D1Re0,D0Re0
59 LSL A0.3,D1Re0,#31
62 OR D0Re0,D0Re0,A0.3
63 LSL A0.3,D1Ar3,#31
66 OR D0Ar4,D0Ar4,A0.3
67 ORS A0.3,D1Re0,D0Re0
Dmemcpy.S14 MOV A0.2, D1Ar1 ! destination pointer
15 MOV A0.3, D1Ar1 ! for return value
25 SETB [A0.2++], D1Re0
30 MOV D0Re0, A0.3
45 SETB [A0.2++], D0Re0
67 SETL [A0.2++], D0Re0, D1Re0
68 SETL [A0.2++], D0Ar6, D1Ar5
71 SETL [A0.2++], D0Re0, D1Re0
72 SETL [A0.2++], D0Ar6, D1Ar5
130 SETL [A0.2++], D0Re0, D1Re0
[all …]
Dmodsi3.S30 MOV A0.2,D1Ar1 ! Save A in A0.2
33 MOV D1Re0,A0.2 ! Recover A
/arch/c6x/kernel/
Dhead.S59 MVKL .S1 OF_DT_HEADER,A0
60 MVKH .S1 OF_DT_HEADER,A0
61 CMPEQ .L1 A10,A0,A0
62 [A0] MV .S1X B10,A4
63 [!A0] MVK .S1 0,A4
66 MVKL .S1 machine_init,A0
67 MVKH .S1 machine_init,A0
68 B .S2X A0
77 MVKL .S1 start_kernel,A0
78 MVKH .S1 start_kernel,A0
[all …]
Dvectors.S24 STW .D2T1 A0,*B15--[2]
25 || MVKL .S1 \handler,A0
26 MVKH .S1 \handler,A0
27 B .S2X A0
28 LDW .D2T1 *++B15[2],A0
51 MVKL .S1 _c_int00,A0 ; branch to _c_int00
52 MVKH .S1 _c_int00,A0
53 B .S2X A0
Dentry.S94 || STDW .D1T1 A1:A0,*A15--[1]
151 LDDW .D1T1 *++A15[1],A1:A0
195 MVKL .S1 schedule,A0
196 MVKH .S1 schedule,A0
197 B .S2X A0
208 MVKL .S1 syscall_trace_entry,A0
209 MVKH .S1 syscall_trace_entry,A0
210 B .S2X A0
244 AND .D1 _TIF_SYSCALL_TRACE,A2,A0
245 [!A0] BNOP .S1 work_pending,5
[all …]
/arch/mips/mm/
Dpage.c42 #define A0 4 macro
236 uasm_i_sd(buf, ZERO, off, A0); in build_clear_store()
238 uasm_i_sw(buf, ZERO, off, A0); in build_clear_store()
249 A0); in build_clear_pref()
252 uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0); in build_clear_pref()
264 uasm_i_cache(buf, Create_Dirty_Excl_D, off, A0); in build_clear_pref()
302 pg_addiu(&buf, A2, A0, off); in build_clear_page()
304 uasm_i_ori(&buf, A2, A0, off); in build_clear_page()
321 pg_addiu(&buf, A0, A0, 2 * off); in build_clear_page()
326 uasm_il_bne(&buf, &r, A0, A2, label_clear_pref); in build_clear_page()
[all …]
/arch/arm/boot/dts/
Dkirkwood-rd88f6281-a.dts10 * This file contains the definitions for the board with the A0 or
19 model = "Marvell RD88f6281 Reference design, with A0 or higher SoC";

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