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Searched refs:D0FrT (Results 1 – 11 of 11) sorted by relevance

/arch/metag/tbx/
Dtbisoft.S74 MOV D0FrT,A0FrP /* Boing entry sequence */
76 SETL [A0StP+#8++],D0FrT,D1RtP
87 ADD D0FrT,A0StP,#TBICTX_AX-TBICTX_DX /* Address AX save area */
90 MSETL [A0StP],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
94 MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
108 GETL D0FrT,D1RtP,[A0FrP++] /* Restore state from frame */
110 MOV A0FrP,D0FrT /* Last memory read completes */
178 MOV D0FrT,A0FrP /* Need save return point */
180 SETL [A0StP++],D0FrT,D1RtP /* Save return to caller */
187 MOV D0FrT,D1Ar1 /* Initial puesdo-frame pointer */
[all …]
Dtbitimer.S66 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
67 CALL D0FrT,#LO(___TBITimeCore) /* and perform register update */
91 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
92 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
115 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
116 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
147 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
148 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
202 MOV PC,D0FrT /* Return quickly */
Dtbipcx.S68 MOV D0FrT,A0FrP /* Boing entry sequence */
70 SETL [A0StP++],D0FrT,D1RtP
72 MOVT D0FrT,#HI(___TBIBoingRTI+4)
73 ADD D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
74 CMP D0Re0,D0FrT
92 ADD D0FrT,A0.2,#TBICTX_AX /* Address AX save area */
93 MSETL [A0.3],D0Re0,D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
98 MSETL [D0FrT],A0StP,A0FrP,A0.2,A0.3 A0_4 /* Save AX regs */
142 MSETL [A1.2],D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7
295 MGETL D0Ar6,D0Ar4,D0Ar2,D0FrT,D0.5,D0.6,D0.7,[A0StP] /* Restore DX */
[all …]
Dtbictx.S59 MOV D0FrT,A0FrP /* Full entry sequence so we */
61 MSETL [A0StP],D0FrT,D0.5,D0.6 /* and preserve our result */
71 MGETL D0FrT,D0.5,D0.6,[A0FrP] /* Full exit sequence */
73 MOV A0FrP,D0FrT
141 MOV D0FrT,TXL1COUNT
143 MSETL [A0.2],D0Ar6,D0FrT /* Save 8*2 bytes */
147 XOR TXL1COUNT,D0FrT,D0FrT
Dtbidefr.S28 MSETL [A0StP++], D0FrT, D0.5
104 GETL D0FrT, D1RtP, [--A0StP]
Dtbicore.S92 SETL [A0StP++],D0FrT,D1RtP /* Save our return address */
97 GETL D0FrT,D1RtP,[--A0StP] /* Restore return address */
/arch/metag/lib/
Dcopy_page.S12 MOV D0FrT,#PAGE_SIZE
18 SUBS D0FrT,D0FrT,#16
Dmodsi3.S15 MOV D0FrT,D1RtP ! Save original return address
17 MOV D1RtP,D0FrT ! Recover return address
29 MOV D0FrT,D1RtP ! Save original return address
32 MOV D1RtP,D0FrT ! Recover return address
Ddiv64.S79 MSETL [A0StP],D0FrT,D0.5
105 GETL D0FrT,D1RtP,[A0StP+#(-16)]
Dmemcpy.S150 LSR D0FrT, D0Ar2, D0Ar6
155 ADD D1Re0, D1Re0, D0FrT
/arch/metag/include/asm/
Dmetag_regs.h91 #define D0FrT D0.4 macro