| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7723.c | 121 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
129 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
180 [HWBLK_MERAM] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 0, 0),
185 [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 28, 0),
216 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7757.c | 63 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR }; enumerator
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
112 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-shx3.c | 62 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR }; enumerator
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
113 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7724.c | 160 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator
167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
220 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
224 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
260 [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0),
281 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7785.c | 66 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator
78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
130 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7366.c | 117 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
205 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7786.c | 68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
138 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7722.c | 123 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator
128 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
191 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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| D | clock-sh7343.c | 114 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
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