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/arch/alpha/lib/
Dev6-copy_user.S52 beq $18, $zerolength # U .. .. .. : U L U L
57 subq $3, 8, $3 # E .. .. .. : L U U L : trip counter
64 EXI( ldbu $1,0($17) ) # .. .. .. L : Keep loads separate from stores
67 nop # E .. .. .. : U L U L
73 EXO( stb $1,-1($16) ) # .. .. .. L :
76 bne $3, $aligndest # U .. .. .. : U L U L
85 EXI( ldq_u $3,0($17) ) # .. L .. .. : Forward fetch for fallthrough code
86 beq $1,$quadaligned # U .. .. .. : U L U L
95 EXI( ldq_u $2,8($17) ) # .. .. .. L :
98 extqh $2,$17,$1 # U .. .. .. : U U L L
[all …]
Dev6-clear_user.S54 beq $0, $zerolength # U .. .. .. : U L U L
61 beq $4, $headalign # U .. .. .. : U L U L
67 EX( ldq_u $5, 0($16) ) # .. .. .. L : load dst word to mask back in
70 addq $16, 8, $16 # E .. .. .. : L U U L
72 EX( stq_u $5, -8($16) ) # .. .. .. L :
75 subq $0, 8, $0 # E .. .. .. : U L U L
89 blt $4, $trailquad # U .. .. .. : U L U L
101 beq $3, $bigalign # U .. .. .. : U L U L : Aligned 0mod64
104 EX( stq_u $31, 0($16) ) # .. .. .. L
107 nop # E .. .. .. : U L U L
[all …]
Dev6-divide.S113 7: stq $1, 0($30) # L :
115 stq $2, 8($30) # L : L U L U
118 stq $0,16($30) # L :
120 LONGIFY(divisor) # E : U L L U
122 stq tmp1,24($30) # L :
125 DIV_ONLY(stq tmp2,32($30)) # L : L U U L
147 bne compare,1b # U : U L U L
152 blt divisor, 2f # U : U L U L
157 bne compare,1b # U : U L U L
179 nop # E : L U L U
[all …]
Dev6-csum_ipv6_magic.S64 ldq_u $0,0($16) # L : Latency: 3
66 ldq_u $1,8($16) # L : Latency: 3
67 sll $19,8,$7 # U : U L U L : 0x00000000 00aabb00
70 ldq_u $5,15($16) # L : Latency: 3
72 ldq_u $2,0($17) # L : U L U L : Latency: 3
76 ldq_u $3,8($17) # L : Latency: 3
77 sll $19,24,$19 # U : U U L U : 0x000000aa bb000000
80 ldq_u $23,15($17) # L : Latency: 3
82 addl $19,$7,$19 # E : U L U L : <sign bits>bbaabb00
87 extqh $5,$6,$5 # U : L U L U
[all …]
Dev6-memchr.S49 ldq_u $1, 0($16) # L : load first quadword Latency=3
50 and $17, 0xff, $17 # E : L L U U : 00000000000000ch
55 lda $3, -1($31) # E : U L L U
60 sll $17, 32, $2 # U : U L L U : chchchch00000000
65 ldq_u $6, -1($5) # L : L U U L : eight or less bytes to search Latency=3
70 or $7, $6, $1 # E : L U L U $1 = quadword starting at $16
80 cmpbge $31, $1, $2 # E : L U L U
85 beq $2, $not_found # U : U L U L
96 ret # L0 : L U L U
110 addq $0, 2, $3 # E : U L U L : 2 cycle stall on $0
[all …]
Dev6-memcpy.S52 ldbu $1, 0($17) # L : grab a byte
55 stb $1, 0($16) # L :
68 ldq $1, 0($17) # L : get 8 bytes
73 stq $1, 0($16) # L : store
91 ldq $4, 8($17) # L : bytes 8..15
92 ldq $5, 16($17) # L : bytes 16..23
96 ldq $3, 24($17) # L : bytes 24..31
102 stq $6, 0($16) # L : bytes 0..7
106 stq $4, 8($16) # L : bytes 8..15
107 stq $5, 16($16) # L : bytes 16..23
[all …]
Dev6-memset.S81 ldq_u $4,0($16) # L : Fetch first partial
92 stq_u $1,0($5) # L : Store result
136 stq $17, 0($5) # L :
163 stq $17, 0($5) # L :
167 stq $17, 8($5) # L :
168 stq $17, 16($5) # L :
171 stq $17, 24($5) # L :
172 stq $17, 32($5) # L :
176 stq $17, 40($5) # L :
177 stq $17, 48($5) # L :
[all …]
Dev6-stxcpy.S74 stq_u t1, 0(a0) # L :
79 ldq_u t1, 0(a1) # L : Latency=3
98 ldq_u t0, 0(a0) # L : Latency=3
108 1: stq_u t1, 0(a0) # L :
129 ldq_u t1, 0(a1) # L : load first src word
134 ldq_u t0, 0(a0) # L :
155 ldq_u t2, 8(a1) # L :
178 stq_u t1, 0(a0) # L : store first output word
209 ldq_u t2, 0(a1) # L : Latency=3 load high word for next time
210 stq_u t1, -8(a0) # L : save the current word (stall)
[all …]
Dev67-strncat.S37 ldq_u $1, 0($16) # L : load first quadword ($16 may be misaligned)
50 $loop: ldq $1, 8($16) # L :
80 stq_u $1, 0($16) # L :
84 stb $31, 8($16) # L :
Dev6-stxncpy.S90 stq_u t0, 0(a0) # L :
95 ldq_u t0, 0(a1) # L :
122 ldq_u t1, 0(a0) # L :
132 1: stq_u t0, 0(a0) # L :
167 ldq_u t1, 0(a1) # L : load first src word
171 ldq_u t0, 0(a0) # L :
197 ldq_u t2, 8(a1) # L : Latency=3 load second src word
214 stq_u t0, 0(a0) # L : store first output word
226 ldq_u t2, 8(a1) # L : read next high-order source word
280 stq_u t0, 0(a0) # L : the null was in the high-order bits
[all …]
/arch/m68k/kernel/
Dhead.S368 #define L(name) .head.S.##name macro
370 #define L(name) .head.S./**/name macro
374 #define L(name) .L##name macro
376 #define L(name) .L/**/name macro
408 L(\name):
425 jbsr L(\name)
544 #define is_040_or_060(lab) btst &CPUTYPE_0460,%pc@(L(cputype)+3); jne lab
545 #define is_not_040_or_060(lab) btst &CPUTYPE_0460,%pc@(L(cputype)+3); jeq lab
546 #define is_040(lab) btst &CPUTYPE_040,%pc@(L(cputype)+3); jne lab
547 #define is_060(lab) btst &CPUTYPE_060,%pc@(L(cputype)+3); jne lab
[all …]
/arch/blackfin/lib/
Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU);
19 R3 = R1.H * R0.L (IS,M);
20 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M);
22 R1.L = R2.H + R1.L;
26 R1.L = R1.L + R3.L;
Dmuldi3.S51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
52 A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
58 A1 = R2.L * R0.L (FU); /* E4 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
19 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU);
Dmemset.S41 R2.L = R2.L + R1.L(NS);
42 R2.H = R2.L + R1.H(NS);
/arch/blackfin/mach-common/
Ddpmc_modes.S20 P0.L = lo(PLL_CTL);
23 W[P0] = R1.L;
39 P0.L = lo(PLL_CTL);
43 w[p0] = R7.L;
69 P3.L = lo(VR_CTL);
79 W[P3] = R4.L;
107 P0.L = lo(PLL_DIV);
109 R0.L = 0xF;
113 P0.L = lo(PLL_CTL);
115 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
[all …]
/arch/blackfin/mach-bf609/
Ddpm.S14 P0.L = LO(PM_STACK);
21 P0.L = LO(DPM0_RESTORE4);
23 P1.L = _bf609_pm_data;
27 P0.L = LO(DPM0_CTL);
29 R3.L = LO(0x00000010);
85 P0.L = LO(PM_STACK);
97 P0.L = LO(DPM0_CTL);
99 R3.L = LO(0x00000008);
134 P0.L = _bf609_pm_data;
136 R1.L = 0xBEEF;
[all …]
/arch/parisc/include/asm/
Dpdcpat.h16 #define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */
66 #define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */
73 #define PDC_PAT_CPU_INFO 0L /* Return CPU config info */
88 #define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */
99 #define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */
142 #define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */
167 #define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
175 #define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */
/arch/sh/include/asm/
Dbitops.h39 : "0" (~0L), "1" (word) in ffz()
59 : "0" (~0L), "1" (word) in __ffs()
81 : "0" (0L), "1" (word)); in ffz()
/arch/blackfin/include/asm/
Dtrace.h62 preg.L = LO(TBUFCTL); \
68 preg.L = LO(TBUFCTL); \
74 preg.L = LO(TBUFCTL); \
82 preg.L = LO(TBUFCTL); \
Ddpmc.h177 FP.L = lo(SYSMMR_BASE);
272 FP.L = lo(SYSMMR_BASE);
367 I0.L = lo(COREMMR_BASE);
375 I1.L = lo(DCPLB_ADDR0);
376 I2.L = lo(DCPLB_DATA0);
377 I3.L = lo(ICPLB_ADDR0);
378 B0.L = lo(ICPLB_DATA0);
379 B1.L = lo(EVT2);
380 B2.L = lo(IMASK);
381 B3.L = lo(TCNTL);
[all …]
/arch/alpha/include/asm/
Dswitch_to.h9 #define switch_to(P,N,L) \ argument
11 (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
/arch/powerpc/kvm/
Dbook3s_32_sr.S65 mtspr SPRN_IBAT##n##L,reg; \
67 mtspr SPRN_DBAT##n##L,reg; \
107 mtspr SPRN_IBAT##n##L,RB; \
111 mtspr SPRN_DBAT##n##L,RB; \
/arch/mips/cavium-octeon/executive/
Dcvmx-l2c.c482 return tag.s.L; in cvmx_l2c_unlock_line()
499 return tag.s.L; in cvmx_l2c_unlock_line()
532 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
541 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
550 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
559 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
568 __BITFIELD_FIELD(uint64_t L:1, /* Line locked */
681 tag.s.L = l2c_tadx_tag.s.lock; in cvmx_l2c_get_tag()
696 tag.s.L = tmp_tag.cn58xx.L; in cvmx_l2c_get_tag()
702 tag.s.L = tmp_tag.cn38xx.L; in cvmx_l2c_get_tag()
[all …]
/arch/parisc/kernel/
Dhpmc.S168 ldil L%PA(os_hpmc_2), rp
183 ldil L%PA(os_hpmc_3),rp
213 ldil L%PA(os_hpmc_4),rp
235 ldil L%PA(os_hpmc_5),rp
283 ldil L%PA(os_hpmc_6),rp
298 ldil L%0xfffc0000,%r4 /* IO_BROADCAST */

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