| /arch/blackfin/mach-bf609/ |
| D | dpm.S | 14 P0.L = LO(PM_STACK);
21 P0.L = LO(DPM0_RESTORE4);
27 P0.L = LO(DPM0_CTL);
29 R3.L = LO(0x00000010);
47 P0.l = LO(SEC_SCI_BASE + SEC_CSID);
52 P1.l = LO(SEC_END);
85 P0.L = LO(PM_STACK);
97 P0.L = LO(DPM0_CTL);
99 R3.L = LO(0x00000008);
|
| /arch/hexagon/kernel/ |
| D | head.S | 42 r24.L = #LO(swapper_pg_dir)
54 r1.l = #LO(PAGE_OFFSET);
75 r1.l = #LO(_end);
76 r2.l = #LO(stext);
110 R1.L = #LO(PAGE_OFFSET >> (22 - 2))
201 {r29.L = #LO(init_thread_union); r0.L = #LO(_THREAD_SIZE); }
208 { r0.L = #LO(__bss_start); r1 = #0; r2.l = #LO(__bss_stop); }
216 r0.l = #LO(__phys_offset);
|
| D | vm_entry.S | 77 R2.L = #LO(_THREAD_SIZE); } \
229 R1.L = #LO(CHandler); \
294 R26.L = #LO(do_work_pending);
382 R26.L = #LO(do_work_pending);
|
| /arch/metag/lib/ |
| D | lshrdi3.S | 23 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
25 OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
31 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
|
| D | ashldi3.S | 23 LSR D0Ar6,D0Re0,D0Ar4 ! TMP= LO >> -(COUNT - 32)
26 LSL D0Re0,D0Re0,D0Ar4 ! LO = LO << COUNT
31 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
32 MOV D0Re0,#0 ! LO = 0
|
| D | ashrdi3.S | 23 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
25 OR D0Re0,D0Re0,D0Ar6 ! LO = LO | TMP
31 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
|
| /arch/mips/pci/ |
| D | ops-nile4.c | 12 #define LO(reg) (reg / 4) macro
40 mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; in nile4_pcibios_config_access()
41 vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0); in nile4_pcibios_config_access()
45 vrc_pciregs[LO(NILE4_PCIERR)] = 0; in nile4_pcibios_config_access()
67 vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; in nile4_pcibios_config_access()
|
| /arch/metag/kernel/ |
| D | head.S | 20 ADD D0Re0,D0Re0,#LO(___pTBIs)
23 ADD D0Re0,D0Re0,#LO(___pTBISegs)
36 ADD A0StP,A0StP,#LO(_init_thread_union)
39 CALL D1RtP,#LO(_metag_start_kernel)
61 ADD A0StP,A0StP,#LO(_secondary_data_stack)
|
| D | ftrace_stub.S | 27 CALL D1RtP,#LO(_ftrace_stub)
42 ADD D0Re0,D0Re0,#LO(_ftrace_trace_function)
45 ADD D1Re0,D1Re0,#LO(_ftrace_stub)
|
| D | user_gateway.S | 41 ADD D1Ar1,D1Ar1,#LO(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
|
| /arch/blackfin/include/asm/ |
| D | trace.h | 62 preg.L = LO(TBUFCTL); \
68 preg.L = LO(TBUFCTL); \
74 preg.L = LO(TBUFCTL); \
82 preg.L = LO(TBUFCTL); \
|
| D | entry.h | 44 preg.l = LO(CHIPID); \
115 P0.L = LO(ILAT); \
145 P0.L = LO(ILAT); \
|
| D | blackfin.h | 54 #define LO(con32) ((con32) & 0xFFFF) macro
|
| /arch/metag/tbx/ |
| D | tbictxfpu.S | 48 ADD D0Ar4, D0Ar4, #LO(METAC_CORE_ID)
54 AND D0Ar4, D0Ar4, #LO(0x0000FFFF)
64 AND D0Re0, D0Re0, #LO(TXDEFR_FPE_FE_BITS>>8)
65 AND D0Ar6, D0Ar6, #LO(TXDEFR_FPE_ICTRL_BITS)
146 AND D1Ar5, D1Ar5, #LO(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
151 ANDMB D1Ar5, D1Ar5, #LO(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
|
| D | tbitimer.S | 67 CALL D0FrT,#LO(___TBITimeCore) /* and perform register update */
92 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
116 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
148 CALL D0FrT,#LO(___TBITimeCore) /* with no register update */
180 ADD A1LbP,A1LbP,#LO(___TBITimes)
|
| D | tbisoft.S | 83 ADD D1Re0,D1Re0,#LO($LSwitchExit)
156 ADD A1LbP,A1LbP,#LO(__exit)
182 ADD A1LbP,A1LbP,#LO(__exit)
194 ADD D1RtP,D1RtP,#LO(___TBIStart)
203 ADD D1Ar1,D1Ar1,#LO($LSwitchExit)
230 ADD A1LbP,A1LbP,#LO(__exit)
|
| D | tbicore.S | 40 ADD A1LbP,A1LbP,#LO(___pTBISegs)
58 ADD A1LbP,A1LbP,#LO(___pTBISegs)
|
| D | tbipcx.S | 73 ADD D0FrT,D0FrT,#LO(___TBIBoingRTI+4)
86 ADD D1Ar5,D1Ar5,#LO(___TBIBoingExit)
109 ADD A0.2,A0.2,#LO($Lpcx_target)
190 ADD A1LbP,A1LbP,#LO(___pTBIs)
316 ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
337 ADD D1Ar3,D1Ar3,#LO(_per_cpu__stack_save)
|
| D | tbiroot.S | 48 ADD A1LbP,A1LbP,#LO(___pTBIs)
|
| D | tbictx.S | 67 CALL D1RtP,#LO(___TBICtxSave)
|
| /arch/blackfin/mach-common/ |
| D | interrupt.S | 167 P0.L = LO(ILAT);
188 R1.L = LO(VEC_HWERR);
200 p0.l = LO(EBIU_ERRMST);
|
| D | cache.S | 83 p0.L = LO(DSPID);
|
| D | entry.S | 367 P4.L = LO(IMEM_CONTROL);
376 P4.L = LO(DMEM_CONTROL);
780 r2 = LO(~0x37) (Z);
891 r1 = LO(~0x8000) (Z);
1194 P4.L = LO(IMEM_CONTROL);
1203 P4.L = LO(DMEM_CONTROL);
|
| /arch/arm/crypto/ |
| D | sha512-core.S_shipped | 60 # define LO 0
65 # define LO 4
154 ldr r7,[r0,#32+LO]
156 ldr r9, [r0,#48+LO]
158 ldr r11, [r0,#56+LO]
165 ldr r5,[r0,#0+LO]
167 ldr r3,[r0,#8+LO]
169 ldr r9, [r0,#16+LO]
171 ldr r11, [r0,#24+LO]
179 ldr r3,[r0,#40+LO]
[all …]
|
| /arch/hexagon/lib/ |
| D | memcpy.S | 222 mask.l = #LO(0x7fffffff);
235 r31.l = #LO(.Lmemcpy_return); /* set up final return pointer */
|