1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_M32R_M32R_H_ 3 #define _ASM_M32R_M32R_H_ 4 5 /* 6 * Renesas M32R processor 7 * 8 * Copyright (C) 2003, 2004 Renesas Technology Corp. 9 */ 10 11 12 /* Chip type */ 13 #if defined(CONFIG_CHIP_XNUX_MP) || defined(CONFIG_CHIP_XNUX2_MP) 14 #include <asm/m32r_mp_fpga.h> 15 #elif defined(CONFIG_CHIP_VDEC2) || defined(CONFIG_CHIP_XNUX2) \ 16 || defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32102) \ 17 || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_M32104) 18 #include <asm/m32102.h> 19 #endif 20 21 /* Platform type */ 22 #if defined(CONFIG_PLAT_M32700UT) 23 #include <asm/m32700ut/m32700ut_pld.h> 24 #include <asm/m32700ut/m32700ut_lan.h> 25 #include <asm/m32700ut/m32700ut_lcd.h> 26 /* for ei_handler:linux/arch/m32r/kernel/entry.S */ 27 #define M32R_INT1ICU_ISTS PLD_ICUISTS 28 #define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE 29 #define M32R_INT0ICU_ISTS M32700UT_LAN_ICUISTS 30 #define M32R_INT0ICU_IRQ_BASE M32700UT_LAN_PLD_IRQ_BASE 31 #define M32R_INT2ICU_ISTS M32700UT_LCD_ICUISTS 32 #define M32R_INT2ICU_IRQ_BASE M32700UT_LCD_PLD_IRQ_BASE 33 #endif /* CONFIG_PLAT_M32700UT */ 34 35 #if defined(CONFIG_PLAT_OPSPUT) 36 #include <asm/opsput/opsput_pld.h> 37 #include <asm/opsput/opsput_lan.h> 38 #include <asm/opsput/opsput_lcd.h> 39 /* for ei_handler:linux/arch/m32r/kernel/entry.S */ 40 #define M32R_INT1ICU_ISTS PLD_ICUISTS 41 #define M32R_INT1ICU_IRQ_BASE OPSPUT_PLD_IRQ_BASE 42 #define M32R_INT0ICU_ISTS OPSPUT_LAN_ICUISTS 43 #define M32R_INT0ICU_IRQ_BASE OPSPUT_LAN_PLD_IRQ_BASE 44 #define M32R_INT2ICU_ISTS OPSPUT_LCD_ICUISTS 45 #define M32R_INT2ICU_IRQ_BASE OPSPUT_LCD_PLD_IRQ_BASE 46 #endif /* CONFIG_PLAT_OPSPUT */ 47 48 #if defined(CONFIG_PLAT_MAPPI2) 49 #include <asm/mappi2/mappi2_pld.h> 50 #endif /* CONFIG_PLAT_MAPPI2 */ 51 52 #if defined(CONFIG_PLAT_MAPPI3) 53 #include <asm/mappi3/mappi3_pld.h> 54 #endif /* CONFIG_PLAT_MAPPI3 */ 55 56 #if defined(CONFIG_PLAT_USRV) 57 #include <asm/m32700ut/m32700ut_pld.h> 58 /* for ei_handler:linux/arch/m32r/kernel/entry.S */ 59 #define M32R_INT1ICU_ISTS PLD_ICUISTS 60 #define M32R_INT1ICU_IRQ_BASE M32700UT_PLD_IRQ_BASE 61 #endif 62 63 #if defined(CONFIG_PLAT_M32104UT) 64 #include <asm/m32104ut/m32104ut_pld.h> 65 /* for ei_handler:linux/arch/m32r/kernel/entry.S */ 66 #define M32R_INT1ICU_ISTS PLD_ICUISTS 67 #define M32R_INT1ICU_IRQ_BASE M32104UT_PLD_IRQ_BASE 68 #endif /* CONFIG_PLAT_M32104 */ 69 70 /* 71 * M32R Register 72 */ 73 74 /* 75 * MMU Register 76 */ 77 78 #define MMU_REG_BASE (0xffff0000) 79 #define ITLB_BASE (0xfe000000) 80 #define DTLB_BASE (0xfe000800) 81 82 #define NR_TLB_ENTRIES CONFIG_TLB_ENTRIES 83 84 #define MATM MMU_REG_BASE /* MMU Address Translation Mode 85 Register */ 86 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */ 87 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */ 88 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */ 89 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual 90 Address Register */ 91 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page 92 Number Register */ 93 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */ 94 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address 95 Register */ 96 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */ 97 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for 98 Instruciton */ 99 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */ 100 101 #define MATM_offset (MATM - MMU_REG_BASE) 102 #define MPSZ_offset (MPSZ - MMU_REG_BASE) 103 #define MASID_offset (MASID - MMU_REG_BASE) 104 #define MESTS_offset (MESTS - MMU_REG_BASE) 105 #define MDEVA_offset (MDEVA - MMU_REG_BASE) 106 #define MDEVP_offset (MDEVP - MMU_REG_BASE) 107 #define MPTB_offset (MPTB - MMU_REG_BASE) 108 #define MSVA_offset (MSVA - MMU_REG_BASE) 109 #define MTOP_offset (MTOP - MMU_REG_BASE) 110 #define MIDXI_offset (MIDXI - MMU_REG_BASE) 111 #define MIDXD_offset (MIDXD - MMU_REG_BASE) 112 113 #define MESTS_IT (1 << 0) /* Instruction TLB miss */ 114 #define MESTS_IA (1 << 1) /* Instruction Access Exception */ 115 #define MESTS_DT (1 << 4) /* Operand TLB miss */ 116 #define MESTS_DA (1 << 5) /* Operand Access Exception */ 117 #define MESTS_DRW (1 << 6) /* Operand Write Exception Flag */ 118 119 /* 120 * PSW (Processor Status Word) 121 */ 122 123 /* PSW bit */ 124 #define M32R_PSW_BIT_SM (7) /* Stack Mode */ 125 #define M32R_PSW_BIT_IE (6) /* Interrupt Enable */ 126 #define M32R_PSW_BIT_PM (3) /* Processor Mode [0:Supervisor,1:User] */ 127 #define M32R_PSW_BIT_C (0) /* Condition */ 128 #define M32R_PSW_BIT_BSM (7+8) /* Backup Stack Mode */ 129 #define M32R_PSW_BIT_BIE (6+8) /* Backup Interrupt Enable */ 130 #define M32R_PSW_BIT_BPM (3+8) /* Backup Processor Mode */ 131 #define M32R_PSW_BIT_BC (0+8) /* Backup Condition */ 132 133 /* PSW bit map */ 134 #define M32R_PSW_SM (1UL<< M32R_PSW_BIT_SM) /* Stack Mode */ 135 #define M32R_PSW_IE (1UL<< M32R_PSW_BIT_IE) /* Interrupt Enable */ 136 #define M32R_PSW_PM (1UL<< M32R_PSW_BIT_PM) /* Processor Mode */ 137 #define M32R_PSW_C (1UL<< M32R_PSW_BIT_C) /* Condition */ 138 #define M32R_PSW_BSM (1UL<< M32R_PSW_BIT_BSM) /* Backup Stack Mode */ 139 #define M32R_PSW_BIE (1UL<< M32R_PSW_BIT_BIE) /* Backup Interrupt Enable */ 140 #define M32R_PSW_BPM (1UL<< M32R_PSW_BIT_BPM) /* Backup Processor Mode */ 141 #define M32R_PSW_BC (1UL<< M32R_PSW_BIT_BC) /* Backup Condition */ 142 143 /* 144 * Direct address to SFR 145 */ 146 147 #include <asm/page.h> 148 #ifdef CONFIG_MMU 149 #define NONCACHE_OFFSET (__PAGE_OFFSET + 0x20000000) 150 #else 151 #define NONCACHE_OFFSET __PAGE_OFFSET 152 #endif /* CONFIG_MMU */ 153 154 #define M32R_ICU_ISTS_ADDR M32R_ICU_ISTS_PORTL+NONCACHE_OFFSET 155 #define M32R_ICU_IPICR_ADDR M32R_ICU_IPICR0_PORTL+NONCACHE_OFFSET 156 #define M32R_ICU_IMASK_ADDR M32R_ICU_IMASK_PORTL+NONCACHE_OFFSET 157 #define M32R_FPGA_CPU_NAME_ADDR M32R_FPGA_CPU_NAME0_PORTL+NONCACHE_OFFSET 158 #define M32R_FPGA_MODEL_ID_ADDR M32R_FPGA_MODEL_ID0_PORTL+NONCACHE_OFFSET 159 #define M32R_FPGA_VERSION_ADDR M32R_FPGA_VERSION0_PORTL+NONCACHE_OFFSET 160 161 #endif /* _ASM_M32R_M32R_H_ */ 162