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Searched refs:MMCR1_TTM0SEL_SH (Results 1 – 6 of 6) sorted by relevance

/arch/powerpc/perf/
Dpower6-pmu.c39 #define MMCR1_TTM0SEL_SH 60 macro
40 #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
Dpower7-pmu.c35 #define MMCR1_TTM0SEL_SH 60 macro
290 << (MMCR1_TTM0SEL_SH - 4 * pmc); in power7_compute_mmcr()
Dpower4-pmu.c55 #define MMCR1_TTM0SEL_SH 62 macro
436 << MMCR1_TTM0SEL_SH; in p4_compute_mmcr()
Dpower5-pmu.c47 #define MMCR1_TTM0SEL_SH 62 macro
460 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; in power5_compute_mmcr()
Dpower5+-pmu.c47 #define MMCR1_TTM0SEL_SH 62 macro
520 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH; in power5p_compute_mmcr()
Dppc970-pmu.c52 #define MMCR1_TTM0SEL_SH 62 macro