Searched refs:MMU_REG_BASE (Results 1 – 5 of 5) sorted by relevance
| /arch/m32r/include/asm/ |
| D | m32r.h | 78 #define MMU_REG_BASE (0xffff0000) macro
84 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
86 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
87 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
88 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
89 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
91 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
93 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
94 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
96 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
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| D | tlbflush.h | 72 : "r" (page), "i" (MMU_REG_BASE), "i" (MSVA_offset), in __flush_tlb_page()
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| /arch/m32r/boot/ |
| D | setup.S | 125 seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
126 or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
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| /arch/m32r/mm/ |
| D | mmu.S | 36 seth r3, #high(MMU_REG_BASE)
221 seth r3, #high(MMU_REG_BASE)
324 seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
325 or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
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| D | fault.c | 406 : "r" (vaddr), "r" (pte_data), "i" (MMU_REG_BASE), in update_mmu_cache()
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