1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4
5 #include <asm/processor-flags.h>
6
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct vm86;
11
12 #include <asm/math_emu.h>
13 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <uapi/asm/sigcontext.h>
16 #include <asm/current.h>
17 #include <asm/cpufeatures.h>
18 #include <asm/page.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
21 #include <asm/msr.h>
22 #include <asm/desc_defs.h>
23 #include <asm/nops.h>
24 #include <asm/special_insns.h>
25 #include <asm/fpu/types.h>
26 #include <asm/unwind_hints.h>
27
28 #include <linux/personality.h>
29 #include <linux/cache.h>
30 #include <linux/threads.h>
31 #include <linux/math64.h>
32 #include <linux/err.h>
33 #include <linux/irqflags.h>
34 #include <linux/mem_encrypt.h>
35
36 /*
37 * We handle most unaligned accesses in hardware. On the other hand
38 * unaligned DMA can be quite expensive on some Nehalem processors.
39 *
40 * Based on this we disable the IP header alignment in network drivers.
41 */
42 #define NET_IP_ALIGN 0
43
44 #define HBP_NUM 4
45 /*
46 * Default implementation of macro that returns current
47 * instruction pointer ("program counter").
48 */
current_text_addr(void)49 static inline void *current_text_addr(void)
50 {
51 void *pc;
52
53 asm volatile("mov $1f, %0; 1:":"=r" (pc));
54
55 return pc;
56 }
57
58 /*
59 * These alignment constraints are for performance in the vSMP case,
60 * but in the task_struct case we must also meet hardware imposed
61 * alignment requirements of the FPU state:
62 */
63 #ifdef CONFIG_X86_VSMP
64 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
65 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
66 #else
67 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
68 # define ARCH_MIN_MMSTRUCT_ALIGN 0
69 #endif
70
71 enum tlb_infos {
72 ENTRIES,
73 NR_INFO
74 };
75
76 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
77 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
78 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
79 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
80 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
81 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
82 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
83
84 /*
85 * CPU type and hardware bug flags. Kept separately for each CPU.
86 * Members of this structure are referenced in head_32.S, so think twice
87 * before touching them. [mj]
88 */
89
90 struct cpuinfo_x86 {
91 __u8 x86; /* CPU family */
92 __u8 x86_vendor; /* CPU vendor */
93 __u8 x86_model;
94 __u8 x86_stepping;
95 #ifdef CONFIG_X86_64
96 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
97 int x86_tlbsize;
98 #endif
99 __u8 x86_virt_bits;
100 __u8 x86_phys_bits;
101 /* CPUID returned core id bits: */
102 __u8 x86_coreid_bits;
103 __u8 cu_id;
104 /* Max extended CPUID function supported: */
105 __u32 extended_cpuid_level;
106 /* Maximum supported CPUID level, -1=no CPUID: */
107 int cpuid_level;
108 __u32 x86_capability[NCAPINTS + NBUGINTS];
109 char x86_vendor_id[16];
110 char x86_model_id[64];
111 /* in KB - valid for CPUS which support this call: */
112 unsigned int x86_cache_size;
113 int x86_cache_alignment; /* In bytes */
114 /* Cache QoS architectural values: */
115 int x86_cache_max_rmid; /* max index */
116 int x86_cache_occ_scale; /* scale to bytes */
117 int x86_power;
118 unsigned long loops_per_jiffy;
119 /* cpuid returned max cores value: */
120 u16 x86_max_cores;
121 u16 apicid;
122 u16 initial_apicid;
123 u16 x86_clflush_size;
124 /* number of cores as seen by the OS: */
125 u16 booted_cores;
126 /* Physical processor id: */
127 u16 phys_proc_id;
128 /* Logical processor id: */
129 u16 logical_proc_id;
130 /* Core id: */
131 u16 cpu_core_id;
132 /* Index into per_cpu list: */
133 u16 cpu_index;
134 u32 microcode;
135 /* Address space bits used by the cache internally */
136 u8 x86_cache_bits;
137 } __randomize_layout;
138
139 struct cpuid_regs {
140 u32 eax, ebx, ecx, edx;
141 };
142
143 enum cpuid_regs_idx {
144 CPUID_EAX = 0,
145 CPUID_EBX,
146 CPUID_ECX,
147 CPUID_EDX,
148 };
149
150 #define X86_VENDOR_INTEL 0
151 #define X86_VENDOR_CYRIX 1
152 #define X86_VENDOR_AMD 2
153 #define X86_VENDOR_UMC 3
154 #define X86_VENDOR_CENTAUR 5
155 #define X86_VENDOR_TRANSMETA 7
156 #define X86_VENDOR_NSC 8
157 #define X86_VENDOR_NUM 9
158
159 #define X86_VENDOR_UNKNOWN 0xff
160
161 /*
162 * capabilities of CPUs
163 */
164 extern struct cpuinfo_x86 boot_cpu_data;
165 extern struct cpuinfo_x86 new_cpu_data;
166
167 extern struct x86_hw_tss doublefault_tss;
168 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
169 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
170
171 #ifdef CONFIG_SMP
172 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
173 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
174 #else
175 #define cpu_info boot_cpu_data
176 #define cpu_data(cpu) boot_cpu_data
177 #endif
178
179 extern const struct seq_operations cpuinfo_op;
180
181 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
182
183 extern void cpu_detect(struct cpuinfo_x86 *c);
184
l1tf_pfn_limit(void)185 static inline unsigned long long l1tf_pfn_limit(void)
186 {
187 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
188 }
189
190 extern void early_cpu_init(void);
191 extern void identify_boot_cpu(void);
192 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
193 extern void print_cpu_info(struct cpuinfo_x86 *);
194 void print_cpu_msr(struct cpuinfo_x86 *);
195 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
196 extern u32 get_scattered_cpuid_leaf(unsigned int level,
197 unsigned int sub_leaf,
198 enum cpuid_regs_idx reg);
199 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
200 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
201
202 extern void detect_extended_topology(struct cpuinfo_x86 *c);
203 extern void detect_ht(struct cpuinfo_x86 *c);
204
205 #ifdef CONFIG_X86_32
206 extern int have_cpuid_p(void);
207 #else
have_cpuid_p(void)208 static inline int have_cpuid_p(void)
209 {
210 return 1;
211 }
212 #endif
native_cpuid(unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)213 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
214 unsigned int *ecx, unsigned int *edx)
215 {
216 /* ecx is often an input as well as an output. */
217 asm volatile("cpuid"
218 : "=a" (*eax),
219 "=b" (*ebx),
220 "=c" (*ecx),
221 "=d" (*edx)
222 : "0" (*eax), "2" (*ecx)
223 : "memory");
224 }
225
226 #define native_cpuid_reg(reg) \
227 static inline unsigned int native_cpuid_##reg(unsigned int op) \
228 { \
229 unsigned int eax = op, ebx, ecx = 0, edx; \
230 \
231 native_cpuid(&eax, &ebx, &ecx, &edx); \
232 \
233 return reg; \
234 }
235
236 /*
237 * Native CPUID functions returning a single datum.
238 */
239 native_cpuid_reg(eax)
native_cpuid_reg(ebx)240 native_cpuid_reg(ebx)
241 native_cpuid_reg(ecx)
242 native_cpuid_reg(edx)
243
244 /*
245 * Friendlier CR3 helpers.
246 */
247 static inline unsigned long read_cr3_pa(void)
248 {
249 return __read_cr3() & CR3_ADDR_MASK;
250 }
251
native_read_cr3_pa(void)252 static inline unsigned long native_read_cr3_pa(void)
253 {
254 return __native_read_cr3() & CR3_ADDR_MASK;
255 }
256
load_cr3(pgd_t * pgdir)257 static inline void load_cr3(pgd_t *pgdir)
258 {
259 write_cr3(__sme_pa(pgdir));
260 }
261
262 /*
263 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
264 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
265 * unrelated to the task-switch mechanism:
266 */
267 #ifdef CONFIG_X86_32
268 /* This is the TSS defined by the hardware. */
269 struct x86_hw_tss {
270 unsigned short back_link, __blh;
271 unsigned long sp0;
272 unsigned short ss0, __ss0h;
273 unsigned long sp1;
274
275 /*
276 * We don't use ring 1, so ss1 is a convenient scratch space in
277 * the same cacheline as sp0. We use ss1 to cache the value in
278 * MSR_IA32_SYSENTER_CS. When we context switch
279 * MSR_IA32_SYSENTER_CS, we first check if the new value being
280 * written matches ss1, and, if it's not, then we wrmsr the new
281 * value and update ss1.
282 *
283 * The only reason we context switch MSR_IA32_SYSENTER_CS is
284 * that we set it to zero in vm86 tasks to avoid corrupting the
285 * stack if we were to go through the sysenter path from vm86
286 * mode.
287 */
288 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
289
290 unsigned short __ss1h;
291 unsigned long sp2;
292 unsigned short ss2, __ss2h;
293 unsigned long __cr3;
294 unsigned long ip;
295 unsigned long flags;
296 unsigned long ax;
297 unsigned long cx;
298 unsigned long dx;
299 unsigned long bx;
300 unsigned long sp;
301 unsigned long bp;
302 unsigned long si;
303 unsigned long di;
304 unsigned short es, __esh;
305 unsigned short cs, __csh;
306 unsigned short ss, __ssh;
307 unsigned short ds, __dsh;
308 unsigned short fs, __fsh;
309 unsigned short gs, __gsh;
310 unsigned short ldt, __ldth;
311 unsigned short trace;
312 unsigned short io_bitmap_base;
313
314 } __attribute__((packed));
315 #else
316 struct x86_hw_tss {
317 u32 reserved1;
318 u64 sp0;
319
320 /*
321 * We store cpu_current_top_of_stack in sp1 so it's always accessible.
322 * Linux does not use ring 1, so sp1 is not otherwise needed.
323 */
324 u64 sp1;
325
326 u64 sp2;
327 u64 reserved2;
328 u64 ist[7];
329 u32 reserved3;
330 u32 reserved4;
331 u16 reserved5;
332 u16 io_bitmap_base;
333
334 } __attribute__((packed));
335 #endif
336
337 /*
338 * IO-bitmap sizes:
339 */
340 #define IO_BITMAP_BITS 65536
341 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
342 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
343 #define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
344 #define INVALID_IO_BITMAP_OFFSET 0x8000
345
346 struct entry_stack {
347 unsigned long words[64];
348 };
349
350 struct entry_stack_page {
351 struct entry_stack stack;
352 } __aligned(PAGE_SIZE);
353
354 struct tss_struct {
355 /*
356 * The fixed hardware portion. This must not cross a page boundary
357 * at risk of violating the SDM's advice and potentially triggering
358 * errata.
359 */
360 struct x86_hw_tss x86_tss;
361
362 /*
363 * The extra 1 is there because the CPU will access an
364 * additional byte beyond the end of the IO permission
365 * bitmap. The extra byte must be all 1 bits, and must
366 * be within the limit.
367 */
368 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
369 } __aligned(PAGE_SIZE);
370
371 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
372
373 /*
374 * sizeof(unsigned long) coming from an extra "long" at the end
375 * of the iobitmap.
376 *
377 * -1? seg base+limit should be pointing to the address of the
378 * last valid byte
379 */
380 #define __KERNEL_TSS_LIMIT \
381 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
382
383 #ifdef CONFIG_X86_32
384 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
385 #else
386 /* The RO copy can't be accessed with this_cpu_xyz(), so use the RW copy. */
387 #define cpu_current_top_of_stack cpu_tss_rw.x86_tss.sp1
388 #endif
389
390 /*
391 * Save the original ist values for checking stack pointers during debugging
392 */
393 struct orig_ist {
394 unsigned long ist[7];
395 };
396
397 #ifdef CONFIG_X86_64
398 DECLARE_PER_CPU(struct orig_ist, orig_ist);
399
400 union irq_stack_union {
401 char irq_stack[IRQ_STACK_SIZE];
402 /*
403 * GCC hardcodes the stack canary as %gs:40. Since the
404 * irq_stack is the object at %gs:0, we reserve the bottom
405 * 48 bytes of the irq stack for the canary.
406 */
407 struct {
408 char gs_base[40];
409 unsigned long stack_canary;
410 };
411 };
412
413 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
414 DECLARE_INIT_PER_CPU(irq_stack_union);
415
416 DECLARE_PER_CPU(char *, irq_stack_ptr);
417 DECLARE_PER_CPU(unsigned int, irq_count);
418 extern asmlinkage void ignore_sysret(void);
419 #else /* X86_64 */
420 #ifdef CONFIG_CC_STACKPROTECTOR
421 /*
422 * Make sure stack canary segment base is cached-aligned:
423 * "For Intel Atom processors, avoid non zero segment base address
424 * that is not aligned to cache line boundary at all cost."
425 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
426 */
427 struct stack_canary {
428 char __pad[20]; /* canary at %gs:20 */
429 unsigned long canary;
430 };
431 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
432 #endif
433 /*
434 * per-CPU IRQ handling stacks
435 */
436 struct irq_stack {
437 u32 stack[THREAD_SIZE/sizeof(u32)];
438 } __aligned(THREAD_SIZE);
439
440 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
441 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
442 #endif /* X86_64 */
443
444 extern unsigned int fpu_kernel_xstate_size;
445 extern unsigned int fpu_user_xstate_size;
446
447 struct perf_event;
448
449 typedef struct {
450 unsigned long seg;
451 } mm_segment_t;
452
453 struct thread_struct {
454 /* Cached TLS descriptors: */
455 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
456 #ifdef CONFIG_X86_32
457 unsigned long sp0;
458 #endif
459 unsigned long sp;
460 #ifdef CONFIG_X86_32
461 unsigned long sysenter_cs;
462 #else
463 unsigned short es;
464 unsigned short ds;
465 unsigned short fsindex;
466 unsigned short gsindex;
467 #endif
468
469 #ifdef CONFIG_X86_64
470 unsigned long fsbase;
471 unsigned long gsbase;
472 #else
473 /*
474 * XXX: this could presumably be unsigned short. Alternatively,
475 * 32-bit kernels could be taught to use fsindex instead.
476 */
477 unsigned long fs;
478 unsigned long gs;
479 #endif
480
481 /* Save middle states of ptrace breakpoints */
482 struct perf_event *ptrace_bps[HBP_NUM];
483 /* Debug status used for traps, single steps, etc... */
484 unsigned long debugreg6;
485 /* Keep track of the exact dr7 value set by the user */
486 unsigned long ptrace_dr7;
487 /* Fault info: */
488 unsigned long cr2;
489 unsigned long trap_nr;
490 unsigned long error_code;
491 #ifdef CONFIG_VM86
492 /* Virtual 86 mode info */
493 struct vm86 *vm86;
494 #endif
495 /* IO permissions: */
496 unsigned long *io_bitmap_ptr;
497 unsigned long iopl;
498 /* Max allowed port in the bitmap, in bytes: */
499 unsigned io_bitmap_max;
500
501 mm_segment_t addr_limit;
502
503 unsigned int sig_on_uaccess_err:1;
504 unsigned int uaccess_err:1; /* uaccess failed */
505
506 /* Floating point and extended processor state */
507 struct fpu fpu;
508 /*
509 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
510 * the end.
511 */
512 };
513
514 /*
515 * Thread-synchronous status.
516 *
517 * This is different from the flags in that nobody else
518 * ever touches our thread-synchronous status, so we don't
519 * have to worry about atomic accesses.
520 */
521 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
522
523 /*
524 * Set IOPL bits in EFLAGS from given mask
525 */
native_set_iopl_mask(unsigned mask)526 static inline void native_set_iopl_mask(unsigned mask)
527 {
528 #ifdef CONFIG_X86_32
529 unsigned int reg;
530
531 asm volatile ("pushfl;"
532 "popl %0;"
533 "andl %1, %0;"
534 "orl %2, %0;"
535 "pushl %0;"
536 "popfl"
537 : "=&r" (reg)
538 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
539 #endif
540 }
541
542 static inline void
native_load_sp0(unsigned long sp0)543 native_load_sp0(unsigned long sp0)
544 {
545 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
546 }
547
native_swapgs(void)548 static inline void native_swapgs(void)
549 {
550 #ifdef CONFIG_X86_64
551 asm volatile("swapgs" ::: "memory");
552 #endif
553 }
554
current_top_of_stack(void)555 static inline unsigned long current_top_of_stack(void)
556 {
557 /*
558 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
559 * and around vm86 mode and sp0 on x86_64 is special because of the
560 * entry trampoline.
561 */
562 return this_cpu_read_stable(cpu_current_top_of_stack);
563 }
564
on_thread_stack(void)565 static inline bool on_thread_stack(void)
566 {
567 return (unsigned long)(current_top_of_stack() -
568 current_stack_pointer) < THREAD_SIZE;
569 }
570
571 #ifdef CONFIG_PARAVIRT
572 #include <asm/paravirt.h>
573 #else
574 #define __cpuid native_cpuid
575
load_sp0(unsigned long sp0)576 static inline void load_sp0(unsigned long sp0)
577 {
578 native_load_sp0(sp0);
579 }
580
581 #define set_iopl_mask native_set_iopl_mask
582 #endif /* CONFIG_PARAVIRT */
583
584 /* Free all resources held by a thread. */
585 extern void release_thread(struct task_struct *);
586
587 unsigned long get_wchan(struct task_struct *p);
588
589 /*
590 * Generic CPUID function
591 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
592 * resulting in stale register contents being returned.
593 */
cpuid(unsigned int op,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)594 static inline void cpuid(unsigned int op,
595 unsigned int *eax, unsigned int *ebx,
596 unsigned int *ecx, unsigned int *edx)
597 {
598 *eax = op;
599 *ecx = 0;
600 __cpuid(eax, ebx, ecx, edx);
601 }
602
603 /* Some CPUID calls want 'count' to be placed in ecx */
cpuid_count(unsigned int op,int count,unsigned int * eax,unsigned int * ebx,unsigned int * ecx,unsigned int * edx)604 static inline void cpuid_count(unsigned int op, int count,
605 unsigned int *eax, unsigned int *ebx,
606 unsigned int *ecx, unsigned int *edx)
607 {
608 *eax = op;
609 *ecx = count;
610 __cpuid(eax, ebx, ecx, edx);
611 }
612
613 /*
614 * CPUID functions returning a single datum
615 */
cpuid_eax(unsigned int op)616 static inline unsigned int cpuid_eax(unsigned int op)
617 {
618 unsigned int eax, ebx, ecx, edx;
619
620 cpuid(op, &eax, &ebx, &ecx, &edx);
621
622 return eax;
623 }
624
cpuid_ebx(unsigned int op)625 static inline unsigned int cpuid_ebx(unsigned int op)
626 {
627 unsigned int eax, ebx, ecx, edx;
628
629 cpuid(op, &eax, &ebx, &ecx, &edx);
630
631 return ebx;
632 }
633
cpuid_ecx(unsigned int op)634 static inline unsigned int cpuid_ecx(unsigned int op)
635 {
636 unsigned int eax, ebx, ecx, edx;
637
638 cpuid(op, &eax, &ebx, &ecx, &edx);
639
640 return ecx;
641 }
642
cpuid_edx(unsigned int op)643 static inline unsigned int cpuid_edx(unsigned int op)
644 {
645 unsigned int eax, ebx, ecx, edx;
646
647 cpuid(op, &eax, &ebx, &ecx, &edx);
648
649 return edx;
650 }
651
652 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
rep_nop(void)653 static __always_inline void rep_nop(void)
654 {
655 asm volatile("rep; nop" ::: "memory");
656 }
657
cpu_relax(void)658 static __always_inline void cpu_relax(void)
659 {
660 rep_nop();
661 }
662
663 /*
664 * This function forces the icache and prefetched instruction stream to
665 * catch up with reality in two very specific cases:
666 *
667 * a) Text was modified using one virtual address and is about to be executed
668 * from the same physical page at a different virtual address.
669 *
670 * b) Text was modified on a different CPU, may subsequently be
671 * executed on this CPU, and you want to make sure the new version
672 * gets executed. This generally means you're calling this in a IPI.
673 *
674 * If you're calling this for a different reason, you're probably doing
675 * it wrong.
676 */
sync_core(void)677 static inline void sync_core(void)
678 {
679 /*
680 * There are quite a few ways to do this. IRET-to-self is nice
681 * because it works on every CPU, at any CPL (so it's compatible
682 * with paravirtualization), and it never exits to a hypervisor.
683 * The only down sides are that it's a bit slow (it seems to be
684 * a bit more than 2x slower than the fastest options) and that
685 * it unmasks NMIs. The "push %cs" is needed because, in
686 * paravirtual environments, __KERNEL_CS may not be a valid CS
687 * value when we do IRET directly.
688 *
689 * In case NMI unmasking or performance ever becomes a problem,
690 * the next best option appears to be MOV-to-CR2 and an
691 * unconditional jump. That sequence also works on all CPUs,
692 * but it will fault at CPL3 (i.e. Xen PV).
693 *
694 * CPUID is the conventional way, but it's nasty: it doesn't
695 * exist on some 486-like CPUs, and it usually exits to a
696 * hypervisor.
697 *
698 * Like all of Linux's memory ordering operations, this is a
699 * compiler barrier as well.
700 */
701 #ifdef CONFIG_X86_32
702 asm volatile (
703 "pushfl\n\t"
704 "pushl %%cs\n\t"
705 "pushl $1f\n\t"
706 "iret\n\t"
707 "1:"
708 : ASM_CALL_CONSTRAINT : : "memory");
709 #else
710 unsigned int tmp;
711
712 asm volatile (
713 UNWIND_HINT_SAVE
714 "mov %%ss, %0\n\t"
715 "pushq %q0\n\t"
716 "pushq %%rsp\n\t"
717 "addq $8, (%%rsp)\n\t"
718 "pushfq\n\t"
719 "mov %%cs, %0\n\t"
720 "pushq %q0\n\t"
721 "pushq $1f\n\t"
722 "iretq\n\t"
723 UNWIND_HINT_RESTORE
724 "1:"
725 : "=&r" (tmp), ASM_CALL_CONSTRAINT : : "cc", "memory");
726 #endif
727 }
728
729 extern void select_idle_routine(const struct cpuinfo_x86 *c);
730 extern void amd_e400_c1e_apic_setup(void);
731
732 extern unsigned long boot_option_idle_override;
733
734 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
735 IDLE_POLL};
736
737 extern void enable_sep_cpu(void);
738 extern int sysenter_setup(void);
739
740 extern void early_trap_init(void);
741 void early_trap_pf_init(void);
742
743 /* Defined in head.S */
744 extern struct desc_ptr early_gdt_descr;
745
746 extern void cpu_set_gdt(int);
747 extern void switch_to_new_gdt(int);
748 extern void load_direct_gdt(int);
749 extern void load_fixmap_gdt(int);
750 extern void load_percpu_segment(int);
751 extern void cpu_init(void);
752
get_debugctlmsr(void)753 static inline unsigned long get_debugctlmsr(void)
754 {
755 unsigned long debugctlmsr = 0;
756
757 #ifndef CONFIG_X86_DEBUGCTLMSR
758 if (boot_cpu_data.x86 < 6)
759 return 0;
760 #endif
761 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
762
763 return debugctlmsr;
764 }
765
update_debugctlmsr(unsigned long debugctlmsr)766 static inline void update_debugctlmsr(unsigned long debugctlmsr)
767 {
768 #ifndef CONFIG_X86_DEBUGCTLMSR
769 if (boot_cpu_data.x86 < 6)
770 return;
771 #endif
772 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
773 }
774
775 extern void set_task_blockstep(struct task_struct *task, bool on);
776
777 /* Boot loader type from the setup header: */
778 extern int bootloader_type;
779 extern int bootloader_version;
780
781 extern char ignore_fpu_irq;
782
783 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
784 #define ARCH_HAS_PREFETCHW
785 #define ARCH_HAS_SPINLOCK_PREFETCH
786
787 #ifdef CONFIG_X86_32
788 # define BASE_PREFETCH ""
789 # define ARCH_HAS_PREFETCH
790 #else
791 # define BASE_PREFETCH "prefetcht0 %P1"
792 #endif
793
794 /*
795 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
796 *
797 * It's not worth to care about 3dnow prefetches for the K6
798 * because they are microcoded there and very slow.
799 */
prefetch(const void * x)800 static inline void prefetch(const void *x)
801 {
802 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
803 X86_FEATURE_XMM,
804 "m" (*(const char *)x));
805 }
806
807 /*
808 * 3dnow prefetch to get an exclusive cache line.
809 * Useful for spinlocks to avoid one state transition in the
810 * cache coherency protocol:
811 */
prefetchw(const void * x)812 static inline void prefetchw(const void *x)
813 {
814 alternative_input(BASE_PREFETCH, "prefetchw %P1",
815 X86_FEATURE_3DNOWPREFETCH,
816 "m" (*(const char *)x));
817 }
818
spin_lock_prefetch(const void * x)819 static inline void spin_lock_prefetch(const void *x)
820 {
821 prefetchw(x);
822 }
823
824 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
825 TOP_OF_KERNEL_STACK_PADDING)
826
827 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
828
829 #define task_pt_regs(task) \
830 ({ \
831 unsigned long __ptr = (unsigned long)task_stack_page(task); \
832 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
833 ((struct pt_regs *)__ptr) - 1; \
834 })
835
836 #ifdef CONFIG_X86_32
837 /*
838 * User space process size: 3GB (default).
839 */
840 #define IA32_PAGE_OFFSET PAGE_OFFSET
841 #define TASK_SIZE PAGE_OFFSET
842 #define TASK_SIZE_LOW TASK_SIZE
843 #define TASK_SIZE_MAX TASK_SIZE
844 #define DEFAULT_MAP_WINDOW TASK_SIZE
845 #define STACK_TOP TASK_SIZE
846 #define STACK_TOP_MAX STACK_TOP
847
848 #define INIT_THREAD { \
849 .sp0 = TOP_OF_INIT_STACK, \
850 .sysenter_cs = __KERNEL_CS, \
851 .io_bitmap_ptr = NULL, \
852 .addr_limit = KERNEL_DS, \
853 }
854
855 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
856
857 #else
858 /*
859 * User space process size. This is the first address outside the user range.
860 * There are a few constraints that determine this:
861 *
862 * On Intel CPUs, if a SYSCALL instruction is at the highest canonical
863 * address, then that syscall will enter the kernel with a
864 * non-canonical return address, and SYSRET will explode dangerously.
865 * We avoid this particular problem by preventing anything executable
866 * from being mapped at the maximum canonical address.
867 *
868 * On AMD CPUs in the Ryzen family, there's a nasty bug in which the
869 * CPUs malfunction if they execute code from the highest canonical page.
870 * They'll speculate right off the end of the canonical space, and
871 * bad things happen. This is worked around in the same way as the
872 * Intel problem.
873 *
874 * With page table isolation enabled, we map the LDT in ... [stay tuned]
875 */
876 #define TASK_SIZE_MAX ((1UL << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
877
878 #define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
879
880 /* This decides where the kernel will search for a free chunk of vm
881 * space during mmap's.
882 */
883 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
884 0xc0000000 : 0xFFFFe000)
885
886 #define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
887 IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
888 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
889 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
890 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
891 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
892
893 #define STACK_TOP TASK_SIZE_LOW
894 #define STACK_TOP_MAX TASK_SIZE_MAX
895
896 #define INIT_THREAD { \
897 .addr_limit = KERNEL_DS, \
898 }
899
900 extern unsigned long KSTK_ESP(struct task_struct *task);
901
902 #endif /* CONFIG_X86_64 */
903
904 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
905 unsigned long new_sp);
906
907 /*
908 * This decides where the kernel will search for a free chunk of vm
909 * space during mmap's.
910 */
911 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
912 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
913
914 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
915
916 /* Get/set a process' ability to use the timestamp counter instruction */
917 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
918 #define SET_TSC_CTL(val) set_tsc_mode((val))
919
920 extern int get_tsc_mode(unsigned long adr);
921 extern int set_tsc_mode(unsigned int val);
922
923 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
924
925 /* Register/unregister a process' MPX related resource */
926 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
927 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
928
929 #ifdef CONFIG_X86_INTEL_MPX
930 extern int mpx_enable_management(void);
931 extern int mpx_disable_management(void);
932 #else
mpx_enable_management(void)933 static inline int mpx_enable_management(void)
934 {
935 return -EINVAL;
936 }
mpx_disable_management(void)937 static inline int mpx_disable_management(void)
938 {
939 return -EINVAL;
940 }
941 #endif /* CONFIG_X86_INTEL_MPX */
942
943 #ifdef CONFIG_CPU_SUP_AMD
944 extern u16 amd_get_nb_id(int cpu);
945 extern u32 amd_get_nodes_per_socket(void);
946 #else
amd_get_nb_id(int cpu)947 static inline u16 amd_get_nb_id(int cpu) { return 0; }
amd_get_nodes_per_socket(void)948 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
949 #endif
950
hypervisor_cpuid_base(const char * sig,uint32_t leaves)951 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
952 {
953 uint32_t base, eax, signature[3];
954
955 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
956 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
957
958 if (!memcmp(sig, signature, 12) &&
959 (leaves == 0 || ((eax - base) >= leaves)))
960 return base;
961 }
962
963 return 0;
964 }
965
966 extern unsigned long arch_align_stack(unsigned long sp);
967 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
968
969 void default_idle(void);
970 #ifdef CONFIG_XEN
971 bool xen_set_default_idle(void);
972 #else
973 #define xen_set_default_idle 0
974 #endif
975
976 void stop_this_cpu(void *dummy);
977 void df_debug(struct pt_regs *regs, long error_code);
978 void microcode_check(void);
979
980 enum l1tf_mitigations {
981 L1TF_MITIGATION_OFF,
982 L1TF_MITIGATION_FLUSH_NOWARN,
983 L1TF_MITIGATION_FLUSH,
984 L1TF_MITIGATION_FLUSH_NOSMT,
985 L1TF_MITIGATION_FULL,
986 L1TF_MITIGATION_FULL_FORCE
987 };
988
989 extern enum l1tf_mitigations l1tf_mitigation;
990
991 enum mds_mitigations {
992 MDS_MITIGATION_OFF,
993 MDS_MITIGATION_FULL,
994 MDS_MITIGATION_VMWERV,
995 };
996
997 enum taa_mitigations {
998 TAA_MITIGATION_OFF,
999 TAA_MITIGATION_UCODE_NEEDED,
1000 TAA_MITIGATION_VERW,
1001 TAA_MITIGATION_TSX_DISABLED,
1002 };
1003
1004 #endif /* _ASM_X86_PROCESSOR_H */
1005