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Searched refs:REG (Results 1 – 25 of 25) sorted by relevance

/arch/m68k/lib/
Dmulsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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Dumodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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Dmodsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
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Ddivsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
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Dudivsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
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/arch/sparc/include/asm/
Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
16 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
20 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
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Dtrap_block.h116 #define __GET_CPUID(REG) \ argument
118 661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
119 srlx REG, 17, REG; \
120 and REG, 0x1f, REG; \
126 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
127 srlx REG, 17, REG; \
128 and REG, 0x3ff, REG; \
131 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
132 srlx REG, 17, REG; \
133 and REG, 0x1f, REG; \
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Dtsb.h77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
78 661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \
82 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
86 661: lduwa [TSB] ASI_N, REG; \
89 lduwa [TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
93 661: ldxa [TSB] ASI_N, REG; \
96 ldxa [TSB] ASI_PHYS_USE_EC, REG; \
/arch/mips/ar7/
Dirq.c46 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) macro
55 REG(ESR_OFFSET(d->irq - ar7_irq_base))); in ar7_unmask_irq()
61 REG(ECR_OFFSET(d->irq - ar7_irq_base))); in ar7_mask_irq()
67 REG(CR_OFFSET(d->irq - ar7_irq_base))); in ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init()
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/arch/arm/mach-netx/include/mach/
Duncompress.h29 #define REG(x) (*(volatile unsigned long *)(x)) macro
47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in putc()
49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in putc()
54 while (REG(base + UART_FR) & FR_TXFF); in putc()
55 REG(base + UART_DR) = c; in putc()
62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) in flush()
64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) in flush()
69 while (REG(base + UART_FR) & FR_BUSY); in flush()
/arch/arm64/kernel/
Dhw_breakpoint.c71 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
73 AARCH64_DBG_READ(N, REG, VAL); \
76 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
78 AARCH64_DBG_WRITE(N, REG, VAL); \
81 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
82 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
83 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
84 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
85 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
86 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
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/arch/arm64/include/asm/
Dhw_breakpoint.h112 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
113 VAL = read_sysreg(dbg##REG##N##_el1);\
116 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
117 write_sysreg(VAL, dbg##REG##N##_el1);\
/arch/sparc/kernel/
Dpsycho_common.h15 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
18 ((unsigned long)(REG)))
Dprom_irqtrans.c102 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
105 ((unsigned long)(REG)))
Dpci_schizo.c74 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
77 ((unsigned long)(REG)))
/arch/sparc/net/
Dbpf_jit_comp_32.c68 #define SETHI(K, REG) \ argument
69 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
70 #define OR_LO(K, REG) \ argument
71 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
121 #define emit_clear(REG) \ argument
123 *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG); \
126 #define emit_set_const(K, REG) \ argument
128 *prog++ = SETHI(K, REG); \
130 *prog++ = OR_LO(K, REG); \
220 #define emit_load_cpu(REG) \ argument
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Dbpf_jit_comp_64.c140 #define SETHI(K, REG) \ argument
141 (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
142 #define OR_LO(K, REG) \ argument
143 (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
653 #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX) argument
654 #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX) argument
/arch/powerpc/xmon/
Dxmon.c196 #define REG "%.16lx" macro
198 #define REG "%.8lx" macro
1221 printf("csum stopped at "REG"\n", adrs+i); in csum()
1359 printf(" data "REG" [", dabr.address); in bpt_cmds()
1504 printf("["REG"] ", sp); in xmon_show_stack()
1510 printf("["REG"] ", sp); in xmon_show_stack()
1631 printf("*** Error reading registers from "REG"\n", in prregs()
1642 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1646 printf("R%.2ld = "REG" R%.2ld = "REG"\n", in prregs()
1667 printf("msr = "REG" cr = %.8lx\n", fp->msr, fp->ccr); in prregs()
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/arch/mips/kvm/
Dtrace.h143 #define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \ argument
144 ((REG) << 3) | (SEL))
145 #define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \ argument
146 ((REG) << 3) | (SEL))
/arch/powerpc/kernel/
Dprocess.c1368 #define REG "%016lx" macro
1372 #define REG "%08lx" macro
1383 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", in show_regs()
1387 printk("MSR: "REG" ", regs->msr); in show_regs()
1392 pr_cont("CFAR: "REG" ", regs->orig_gpr3); in show_regs()
1395 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); in show_regs()
1397 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); in show_regs()
1410 pr_cont(REG " ", regs->gpr[i]); in show_regs()
1420 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); in show_regs()
1421 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); in show_regs()
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/arch/powerpc/include/asm/
Dreg.h1186 #define MTFSF_L(REG) \ argument
1187 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1189 #define MTFSF_L(REG) mtfsf 0xff, (REG) argument
/arch/arc/kernel/
Dentry-compact.S337 ; Restore REG File. In case multiple Events outstanding,
/arch/m68k/ifpsp060/src/
Disp.S916 # MODE and REG are taken from the EXC_OPWORD.
923 # jump to the corresponding function for each {MODE,REG} pair.
Dpfpsp.S4575 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
4583 # jump to the corresponding function for each {MODE,REG} pair.
Dfpsp.S18526 # currently, MODE and REG are taken from the EXC_OPWORD. this could be
18534 # jump to the corresponding function for each {MODE,REG} pair.