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Searched refs:RS (Results 1 – 14 of 14) sorted by relevance

/arch/mips/mm/
Duasm-mips.c52 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
53 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
54 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
55 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
56 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
59 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
60 [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
61 [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
[all …]
Duasm-micromips.c44 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
45 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
46 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
47 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
48 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
50 [insn_bgez] = {M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM},
52 [insn_bltz] = {M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM},
54 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
55 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
56 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
[all …]
Duasm.c17 RS = 0x001, enumerator
/arch/powerpc/xmon/
Dppc-opc.c577 #define RS RC + 1 macro
578 #define RT RS
580 #define RD RS
585 #define RSQ RS + 1
3272 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3275 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
3277 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
3278 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
3280 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
3281 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
[all …]
/arch/powerpc/platforms/powermac/
Dtime.c54 #define RS 0x200 /* skip between registers */ macro
55 #define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */
56 #define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */
57 #define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */
58 #define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */
59 #define ACR (11*RS) /* Auxiliary control register */
60 #define IFR (13*RS) /* Interrupt flag register */
/arch/arm/boot/dts/
Dkirkwood-openrd.dtsi63 * SelRS232or485 selects between RS-232 or RS-485
66 * Low: RS-232
67 * High: RS-485
Daspeed-bmc-opp-romulus.dts57 /* Rear RS-232 connector */
/arch/powerpc/include/asm/
Dasm-compat.h34 #define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS) argument
Dppc_asm.h405 #define MTOCRF(FXM, RS) \
407 mtcrf (FXM), RS; \
409 mtocrf (FXM), RS; \
/arch/m68k/fpsp040/
Dstan.S236 fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3))
241 faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3))
274 fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3))
279 faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
/arch/cris/arch-v10/drivers/
DKconfig382 bool "RS-485 support"
385 Enables support for RS-485 serial communication. For a primer on
386 RS-485, see <http://en.wikipedia.org/wiki/Rs485>
389 bool "RS-485 mode on PA"
397 int "RS-485 mode on PA bit"
/arch/cris/arch-v32/drivers/
DKconfig32 bool "RS-485 support"
35 Enables support for RS-485 serial communication.
/arch/powerpc/
DKconfig891 have an IBM RS/6000 or pSeries machine, say Y. If you have an
962 # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
/arch/m68k/ifpsp060/src/
Dfplsp.S5822 fmul.x %fp0,%fp2 # RS(P1+S(P2+SP3))
5826 fadd.x %fp2,%fp0 # R+RS(P1+S(P2+SP3))
5859 fmul.x %fp1,%fp2 # RS(P1+S(P2+SP3))
5863 fadd.x %fp2,%fp1 # R+RS(P1+S(P2+SP3))