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Searched refs:SICB_IMASK1 (Results 1 – 3 of 3) sorted by relevance

/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h53 #define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */ macro
DcdefBF561.h70 #define bfin_read_SICB_IMASK1() bfin_read32(SICB_IMASK1)
71 #define bfin_write_SICB_IMASK1(val) bfin_write32(SICB_IMASK1,val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1513 D32(SICB_IMASK1); in bfin_debug_mmrs_init()