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Searched refs:SICB_IWR0 (Results 1 – 4 of 4) sorted by relevance

/arch/blackfin/mach-bf561/
Dsecondary.S148 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h64 #define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */ macro
DcdefBF561.h92 #define bfin_read_SICB_IWR0() bfin_read32(SICB_IWR0)
93 #define bfin_write_SICB_IWR0(val) bfin_write32(SICB_IWR0,val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1516 D32(SICB_IWR0); in bfin_debug_mmrs_init()