| /arch/powerpc/lib/ |
| D | feature-fixups-test.S | 194 #define MAKE_MACRO_TEST(TYPE) \ argument
195 globl(ftr_fixup_test_ ##TYPE##_macros) \
198 BEGIN_##TYPE##_SECTION \
202 END_##TYPE##_SECTION(0, 1) \
206 BEGIN_##TYPE##_SECTION \
210 END_##TYPE##_SECTION(0, 0) \
214 BEGIN_##TYPE##_SECTION \
217 BEGIN_##TYPE##_SECTION_NESTED(80) \
220 END_##TYPE##_SECTION_NESTED(0, 1, 80) \
223 END_##TYPE##_SECTION(0, 0) \
[all …]
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| /arch/sparc/math-emu/ |
| D | math_32.c | 282 #define TYPE(dummy, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru <… in do_one_mathemu() macro
298 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break; in do_one_mathemu()
302 case FDIVQ: TYPE(3,3,1,3,1,3,1); break; in do_one_mathemu()
303 case FDMULQ: TYPE(3,3,1,2,1,2,1); break; in do_one_mathemu()
304 case FQTOS: TYPE(3,1,1,3,1,0,0); break; in do_one_mathemu()
305 case FQTOD: TYPE(3,2,1,3,1,0,0); break; in do_one_mathemu()
306 case FITOQ: TYPE(3,3,1,1,0,0,0); break; in do_one_mathemu()
307 case FSTOQ: TYPE(3,3,1,1,1,0,0); break; in do_one_mathemu()
308 case FDTOQ: TYPE(3,3,1,2,1,0,0); break; in do_one_mathemu()
309 case FQTOI: TYPE(3,1,0,3,1,0,0); break; in do_one_mathemu()
[all …]
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| D | math_64.c | 176 #define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << … in do_mathemu() macro
198 case FABSQ: TYPE(3,3,0,3,0,0,0); break; in do_mathemu()
199 case FSQRTQ: TYPE(3,3,1,3,1,0,0); break; in do_mathemu()
203 case FDIVQ: TYPE(3,3,1,3,1,3,1); break; in do_mathemu()
204 case FDMULQ: TYPE(3,3,1,2,1,2,1); break; in do_mathemu()
205 case FQTOX: TYPE(3,2,0,3,1,0,0); break; in do_mathemu()
206 case FXTOQ: TYPE(3,3,1,2,0,0,0); break; in do_mathemu()
207 case FQTOS: TYPE(3,1,1,3,1,0,0); break; in do_mathemu()
208 case FQTOD: TYPE(3,2,1,3,1,0,0); break; in do_mathemu()
209 case FITOQ: TYPE(3,3,1,1,0,0,0); break; in do_mathemu()
[all …]
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| /arch/sparc/include/asm/ |
| D | asm.h | 10 #define BRANCH32(TYPE, PREDICT, DEST) \ argument
11 TYPE,PREDICT %icc, DEST
12 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ argument
13 TYPE,a,PREDICT %icc, DEST
23 #define BRANCH32(TYPE, PREDICT, DEST) \ argument
24 TYPE DEST
25 #define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \ argument
26 TYPE,a DEST
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| D | vio.h | 471 #define viodbg(TYPE, f, a...) \ argument
472 do { if (vio->debug & VIO_DEBUG_##TYPE) \
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| /arch/x86/kernel/fpu/ |
| D | init.c | 142 #define TYPE_ALIGN(TYPE) offsetof(struct { char x; TYPE test; }, test) argument
150 #define CHECK_MEMBER_AT_END_OF(TYPE, MEMBER) \ argument
151 BUILD_BUG_ON(sizeof(TYPE) != ALIGN(offsetofend(TYPE, MEMBER), \
152 TYPE_ALIGN(TYPE)))
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| /arch/metag/include/asm/ |
| D | switch.h | 19 #define __METAG_SW_ENCODING(TYPE) (0xaf000000 | (__METAG_SW_##TYPE)) argument
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| /arch/mips/include/asm/octeon/ |
| D | cvmx.h | 211 #define CVMX_BUILD_WRITE64(TYPE, ST) \ argument
212 static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
214 *CASTPTR(volatile TYPE##_t, addr) = val; \
225 #define CVMX_BUILD_READ64(TYPE, LT) \ argument
226 static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
228 return *CASTPTR(volatile TYPE##_t, addr); \
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| /arch/mn10300/include/asm/ |
| D | cpu-regs.h | 30 #define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR)) argument
31 #define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR)) argument
33 #define __SYSREG(ADDR, TYPE) ADDR
34 #define __SYSREGC(ADDR, TYPE) ADDR
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| /arch/alpha/include/asm/ |
| D | pal.h | 18 #define __CALL_PAL_R0(NAME, TYPE) \ argument
19 extern inline TYPE NAME(void) \
21 register TYPE __r0 __asm__("$0"); \
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| D | io.h | 147 #define REMAP1(TYPE, NAME, QUAL) \ argument
148 static inline TYPE generic_##NAME(QUAL void __iomem *addr) \
153 #define REMAP2(TYPE, NAME, QUAL) \ argument
154 static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
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| /arch/mips/net/ |
| D | bpf_jit_asm.S | 46 #define is_offset_negative(TYPE) \ argument
49 bgtz t0, bpf_slow_path_##TYPE##_neg; \
52 #define is_offset_in_header(SIZE, TYPE) \ argument
56 bgtz t0, bpf_slow_path_##TYPE; \
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| /arch/mips/pci/ |
| D | pci-vr41xx.h | 106 #define TYPE 0x6U macro
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| /arch/arm64/kernel/ |
| D | cpufeature.c | 75 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
80 .type = TYPE, \
87 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
88 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
91 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ argument
92 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
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| /arch/sparc/kernel/ |
| D | ldc.c | 176 #define ldcdbg(TYPE, f, a...) \ argument
177 do { if (lp->cfg.debug & LDC_DEBUG_##TYPE) \
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| /arch/m68k/ifpsp060/src/ |
| D | fpsp.S | 4061 # bftst %d0{&7:&3} # test TYPE
4066 # TYPE == 0: General instructions #
4254 # TYPE == 1: FDB<cc>, FS<cc>, FTRAP<cc>
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