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Searched refs:__HEXAGON_C_WB_L2 (Results 1 – 3 of 3) sorted by relevance

/arch/hexagon/include/asm/
Dvm_mmu.h78 #define __HEXAGON_C_WB_L2 0x7 /* Write-back, with L2 */ macro
85 #define CACHE_DEFAULT __HEXAGON_C_WB_L2
/arch/hexagon/kernel/
Dhead.S66 | __HEXAGON_C_WB_L2 << 6 \
Dvm_init_segtable.S37 | __HEXAGON_C_WB_L2 << 6 \