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Searched refs:__raw_readl (Results 1 – 25 of 302) sorted by relevance

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/arch/mips/sgi-ip22/
Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/arch/sh/boards/mach-dreamcast/
Drtc.c38 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
39 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
41 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
42 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
66 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
67 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
69 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
70 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/arch/arm/mach-pxa/
Dsmemc.c22 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
23 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
24 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
25 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
26 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
27 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
28 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
29 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
/arch/arm/mach-s3c24xx/include/mach/
Dpm-core.h21 unsigned long tmp = __raw_readl(S3C2410_CLKCON); in s3c_pm_debug_init_uart()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
72 __raw_readl(S3C2410_EINTPEND)); in s3c_pm_arch_show_resume_irqs()
74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
77 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), in s3c_pm_arch_show_resume_irqs()
/arch/arm/mach-ks8695/
Dpci.c133 cmdstat = __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS); in ks8695_pci_fault()
209 printk(KERN_INFO "PCI: CRCFID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFID)); in ks8695_show_pciregs()
210 printk(KERN_INFO "PCI: CRCFCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFCS)); in ks8695_show_pciregs()
211 printk(KERN_INFO "PCI: CRCFRV = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFRV)); in ks8695_show_pciregs()
212 printk(KERN_INFO "PCI: CRCFLT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFLT)); in ks8695_show_pciregs()
213 printk(KERN_INFO "PCI: CRCBMA = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCBMA)); in ks8695_show_pciregs()
214 printk(KERN_INFO "PCI: CRCSID = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCSID)); in ks8695_show_pciregs()
215 printk(KERN_INFO "PCI: CRCFIT = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_CRCFIT)); in ks8695_show_pciregs()
217 printk(KERN_INFO "PCI: PBM = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBM)); in ks8695_show_pciregs()
218 printk(KERN_INFO "PCI: PBCS = %08x\n", __raw_readl(KS8695_PCI_VA + KS8695_PBCS)); in ks8695_show_pciregs()
[all …]
/arch/mips/loongson32/common/
Dirq.c32 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
41 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
50 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
52 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
61 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
72 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
78 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
84 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/arch/arm/mach-iop13xx/
Dpci.c155 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) in iop13xx_atu_function()
161 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) in iop13xx_atu_function()
245 status = __raw_readl(IOP13XX_ATUX_ATUISR); in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
355 status = __raw_readl(IOP13XX_ATUE_ATUISR); in iop13xx_atue_pci_status()
366 status = __raw_readl(IOP13XX_ATUE_PIE_STS) & in iop13xx_atue_pci_status()
367 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK)); in iop13xx_atue_pci_status()
371 __raw_readl(IOP13XX_ATUE_PIE_STS)); in iop13xx_atue_pci_status()
375 __raw_readl(IOP13XX_ATUE_PIE_STS)); in iop13xx_atue_pci_status()
377 __raw_readl(IOP13XX_ATUE_PIE_MSK)); in iop13xx_atue_pci_status()
[all …]
/arch/arm/mach-mmp/
Dpm-mmp2.c49 data |= __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
54 data = ~data & __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
70 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable()
86 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable()
107 val = __raw_readl(MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable()
118 idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); in mmp2_pm_enter_lowpower_mode()
119 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode()
164 temp = __raw_readl(MMP2_ICU_INT4_MASK); in mmp2_pm_enter()
170 temp = __raw_readl(APMU_SRAM_PWR_DWN); in mmp2_pm_enter()
239 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init()
[all …]
Dpm-pxa910.c114 awucrm |= __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
118 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake()
123 awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
127 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake()
138 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
139 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
194 reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); in pxa910_pm_enter()
198 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
217 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
264 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init()
[all …]
/arch/mips/alchemy/common/
Dusb.c101 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
102 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
130 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
138 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
147 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ohci_control()
152 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
167 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
172 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
179 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
184 r = __raw_readl(base + USB_INT_ENABLE); in __au1300_ehci_control()
[all …]
/arch/arm/plat-samsung/
Dpm-gpio.c35 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save()
36 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save()
42 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
43 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
72 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save()
73 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save()
74 chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP); in samsung_gpio_pm_2bit_save()
129 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
130 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
200 chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_4bit_save()
[all …]
Dpm-debug.c71 save->ulcon = __raw_readl(regs + S3C2410_ULCON); in s3c_pm_save_uarts()
72 save->ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_save_uarts()
73 save->ufcon = __raw_readl(regs + S3C2410_UFCON); in s3c_pm_save_uarts()
74 save->umcon = __raw_readl(regs + S3C2410_UMCON); in s3c_pm_save_uarts()
75 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); in s3c_pm_save_uarts()
78 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); in s3c_pm_save_uarts()
/arch/mips/pci/
Dops-tx4927.c73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB) in check_abort()
86 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
114 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
234 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
235 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
236 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
243 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
311 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
[all …]
Dpci-ar724x.c59 reset = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_RESET); in ar724x_pci_check_link()
85 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
107 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
127 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
196 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
218 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
237 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & in ar724x_pci_irq_handler()
238 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
260 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
264 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
[all …]
/arch/arm/mach-cns3xxx/
Dpm.c20 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
29 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down()
60 u32 reg = __raw_readl(PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
108 u32 reg = __raw_readl(PM_CLK_CTRL_REG); in cns3xxx_cpu_clock()
/arch/arm/mach-davinci/
Dpsc.c44 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); in davinci_psc_is_clk_active()
100 mdctl = __raw_readl(psc_base + MDCTL + 4 * id); in davinci_psc_config()
107 pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain); in davinci_psc_config()
109 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); in davinci_psc_config()
117 epcpr = __raw_readl(psc_base + EPCPR); in davinci_psc_config()
120 pdctl = __raw_readl(psc_base + PDCTL + 4 * domain); in davinci_psc_config()
129 ptstat = __raw_readl(psc_base + PTSTAT); in davinci_psc_config()
133 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id); in davinci_psc_config()
Dpm.c54 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
61 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
67 val = __raw_readl(pm_config.deepsleep_reg); in davinci_pm_suspend()
78 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
83 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
91 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
99 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
/arch/arm/common/
Dit8152.c40 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | in it8152_mask_irq()
44 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | in it8152_mask_irq()
48 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | in it8152_mask_irq()
59 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & in it8152_unmask_irq()
63 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & in it8152_unmask_irq()
67 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & in it8152_unmask_irq()
105 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); in it8152_irq_demux()
106 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); in it8152_irq_demux()
107 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); in it8152_irq_demux()
117 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); in it8152_irq_demux()
[all …]
/arch/sh/kernel/cpu/sh4a/
Dubc.c53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
72 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask()
80 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask()
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
124 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()
Dsmp-shx3.c37 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ in ipi_interrupt_handler()
54 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
93 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
96 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
105 return __raw_readl(0xff000048); /* CPIDR */ in shx3_smp_processor_id()
120 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_update_boot_vector()
Dclock-sh7770.c24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f); in module_clk_recalc()
43 int idx = (__raw_readl(FRQCR) & 0x000f); in bus_clk_recalc()
53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f); in cpu_clk_recalc()
Dclock-sh7780.c27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; in master_clk_init()
36 int idx = (__raw_readl(FRQCR) & 0x0003); in module_clk_recalc()
46 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007); in bus_clk_recalc()
56 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001); in cpu_clk_recalc()
79 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007); in shyway_clk_recalc()
/arch/sh/boards/mach-cayman/
Dirq.c68 mask = __raw_readl(reg); in enable_cayman_irq()
86 mask = __raw_readl(reg); in disable_cayman_irq()
106 status = __raw_readl(EPLD_STATUS_BASE) & in cayman_irq_demux()
107 __raw_readl(EPLD_MASK_BASE) & 0xff; in cayman_irq_demux()
123 status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & in cayman_irq_demux()
124 __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; in cayman_irq_demux()
/arch/arm/mach-s3c24xx/
Dsimtec-pm.c58 gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; in pm_simtec_init()
59 gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; in pm_simtec_init()
60 gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); in pm_simtec_init()
Dpm-s3c2410.c50 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); in s3c2410_pm_prepare()
51 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); in s3c2410_pm_prepare()
61 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare()
77 calc += __raw_readl(base+ptr); in s3c2410_pm_prepare()
106 tmp = __raw_readl(S3C2410_GSTATUS2); in s3c2410_pm_resume()

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