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Searched refs:cfg (Results 1 – 25 of 149) sorted by relevance

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/arch/x86/pci/
Dmmconfig-shared.c35 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
37 if (cfg->res.parent) in pci_mmconfig_remove()
38 release_resource(&cfg->res); in pci_mmconfig_remove()
39 list_del(&cfg->list); in pci_mmconfig_remove()
40 kfree(cfg); in pci_mmconfig_remove()
45 struct pci_mmcfg_region *cfg, *tmp; in free_all_mmcfg() local
48 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) in free_all_mmcfg()
49 pci_mmconfig_remove(cfg); in free_all_mmcfg()
54 struct pci_mmcfg_region *cfg; in list_add_sorted() local
57 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) { in list_add_sorted()
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Dmmconfig_64.c21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
99 static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg) in mcfg_ioremap() argument
105 start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
106 num_buses = cfg->end_bus - cfg->start_bus + 1; in mcfg_ioremap()
110 addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
116 struct pci_mmcfg_region *cfg; in pci_mmcfg_arch_init() local
118 list_for_each_entry(cfg, &pci_mmcfg_list, list) in pci_mmcfg_arch_init()
119 if (pci_mmcfg_arch_map(cfg)) { in pci_mmcfg_arch_init()
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/arch/arm/mach-davinci/
Dmux.c38 const struct mux_config *cfg; in davinci_cfg_reg() local
58 cfg = &soc_info->pinmux_pins[index]; in davinci_cfg_reg()
60 if (cfg->name == NULL) { in davinci_cfg_reg()
66 if (cfg->mask) { in davinci_cfg_reg()
70 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
72 mask = (cfg->mask << cfg->mask_offset); in davinci_cfg_reg()
76 tmp2 = (cfg->mode << cfg->mask_offset); in davinci_cfg_reg()
82 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
88 pr_warn("initialized %s\n", cfg->name); in davinci_cfg_reg()
93 if (cfg->debug || warn) { in davinci_cfg_reg()
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/arch/arm/plat-samsung/include/plat/
Dcpu-freq-core.h171 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
174 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
177 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
180 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
185 struct s3c_cpufreq_config *cfg,
188 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
189 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
190 void (*set_divs)(struct s3c_cpufreq_config *cfg);
191 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
215 extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
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/arch/mips/loongson64/loongson-3/
Dhpet.c35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
87 int cfg; in hpet_set_state_periodic() local
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/arch/arm/mach-omap2/
Domap-smp.c55 static struct omap_smp_config cfg; variable
76 return cfg.scu_base; in omap4_get_scu_base()
207 cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap4_boot_secondary()
293 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); in omap4_smp_init_cpus()
294 BUG_ON(!cfg.scu_base); in omap4_smp_init_cpus()
295 ncores = scu_get_core_count(cfg.scu_base); in omap4_smp_init_cpus()
339 released = readl_relaxed(cfg.wakeupgen_base + in omap4_smp_maybe_reset_cpu1()
348 cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base + in omap4_smp_maybe_reset_cpu1()
395 cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa; in omap4_smp_prepare_cpus()
396 cfg.startup_addr = c->startup_addr; in omap4_smp_prepare_cpus()
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/arch/mips/oprofile/
Dop_model_loongson2.c52 static void loongson2_reg_setup(struct op_counter_config *cfg) in loongson2_reg_setup() argument
63 if (cfg[0].enabled) { in loongson2_reg_setup()
64 ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event); in loongson2_reg_setup()
65 reg.reset_counter1 = 0x80000000ULL - cfg[0].count; in loongson2_reg_setup()
68 if (cfg[1].enabled) { in loongson2_reg_setup()
69 ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event); in loongson2_reg_setup()
70 reg.reset_counter2 = 0x80000000ULL - cfg[1].count; in loongson2_reg_setup()
73 if (cfg[0].enabled || cfg[1].enabled) { in loongson2_reg_setup()
75 if (cfg[0].kernel || cfg[1].kernel) in loongson2_reg_setup()
77 if (cfg[0].user || cfg[1].user) in loongson2_reg_setup()
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/arch/mips/kernel/
Dcevt-sb1250.c44 void __iomem *cfg; in sibyte_shutdown() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
49 __raw_writeq(0, cfg); in sibyte_shutdown()
57 void __iomem *cfg, *init; in sibyte_set_periodic() local
59 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
62 __raw_writeq(0, cfg); in sibyte_set_periodic()
64 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
72 void __iomem *cfg, *init; in sibyte_next_event() local
74 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
77 __raw_writeq(0, cfg); in sibyte_next_event()
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Dcevt-bcm1480.c47 void __iomem *cfg, *init; in sibyte_set_periodic() local
49 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
52 __raw_writeq(0, cfg); in sibyte_set_periodic()
54 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
61 void __iomem *cfg; in sibyte_shutdown() local
63 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_shutdown()
66 __raw_writeq(0, cfg); in sibyte_shutdown()
73 void __iomem *cfg, *init; in sibyte_next_event() local
75 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_next_event()
78 __raw_writeq(0, cfg); in sibyte_next_event()
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Dsegment.c16 static void build_segment_config(char *str, unsigned int cfg) in build_segment_config() argument
24 am = (cfg & MIPS_SEGCFG_AM) >> MIPS_SEGCFG_AM_SHIFT; in build_segment_config()
32 if ((am == 0) || (am > 3) || (cfg & MIPS_SEGCFG_EU)) in build_segment_config()
34 ((cfg & MIPS_SEGCFG_PA) >> MIPS_SEGCFG_PA_SHIFT)); in build_segment_config()
40 ((cfg & MIPS_SEGCFG_C) >> MIPS_SEGCFG_C_SHIFT)); in build_segment_config()
46 ((cfg & MIPS_SEGCFG_EU) >> MIPS_SEGCFG_EU_SHIFT)); in build_segment_config()
/arch/arm/mach-s3c24xx/
Dcpufreq-utils.c33 void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) in s3c2410_cpufreq_setrefresh() argument
35 struct s3c_cpufreq_board *board = cfg->board; in s3c2410_cpufreq_setrefresh()
46 refresh = (cfg->freq.hclk / 100) * (board->refresh / 10); in s3c2410_cpufreq_setrefresh()
62 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) in s3c2410_set_fvco() argument
64 if (!IS_ERR(cfg->mpll)) in s3c2410_set_fvco()
65 clk_set_rate(cfg->mpll, cfg->pll.frequency); in s3c2410_set_fvco()
Diotiming-s3c2412.c95 static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg, in s3c2412_calc_bank() argument
98 unsigned int hclk = cfg->freq.hclk_tns; in s3c2412_calc_bank()
118 struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_debugfs() argument
142 int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_calc() argument
154 ret = s3c2412_calc_bank(cfg, bt); in s3c2412_iotiming_calc()
175 void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_set() argument
205 static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_getbank() argument
209 unsigned long clk = cfg->freq.hclk_tns; /* ssmc clock??? */ in s3c2412_iotiming_getbank()
232 int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, in s3c2412_iotiming_get() argument
252 s3c2412_iotiming_getbank(cfg, bt, bank); in s3c2412_iotiming_get()
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/arch/arm/mach-omap1/
Dmux.c346 static int omap1_cfg_reg(const struct pin_config *cfg) in omap1_cfg_reg() argument
355 if (cfg->mux_reg) { in omap1_cfg_reg()
359 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
362 mask = (0x7 << cfg->mask_offset); in omap1_cfg_reg()
366 tmp2 = (cfg->mask << cfg->mask_offset); in omap1_cfg_reg()
372 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
378 if (cfg->pu_pd_reg && cfg->pull_val) { in omap1_cfg_reg()
380 pu_pd_orig = omap_readl(cfg->pu_pd_reg); in omap1_cfg_reg()
381 mask = 1 << cfg->pull_bit; in omap1_cfg_reg()
383 if (cfg->pu_pd_val) { in omap1_cfg_reg()
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/arch/arm64/kernel/
Dpci.c75 struct pci_config_window *cfg; /* config space mapping */ member
80 struct pci_config_window *cfg = bus->sysdata; in acpi_pci_bus_find_domain_nr() local
81 struct acpi_device *adev = to_acpi_device(cfg->parent); in acpi_pci_bus_find_domain_nr()
90 struct pci_config_window *cfg = bridge->bus->sysdata; in pcibios_root_bridge_prepare() local
91 struct acpi_device *adev = to_acpi_device(cfg->parent); in pcibios_root_bridge_prepare()
127 struct pci_config_window *cfg; in pci_acpi_setup_ecam_mapping() local
144 cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); in pci_acpi_setup_ecam_mapping()
145 if (IS_ERR(cfg)) { in pci_acpi_setup_ecam_mapping()
147 PTR_ERR(cfg)); in pci_acpi_setup_ecam_mapping()
151 return cfg; in pci_acpi_setup_ecam_mapping()
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/arch/ia64/kernel/
Dirq_ia64.c130 struct irq_cfg *cfg = &irq_cfg[irq]; in __bind_irq_vector() local
138 if ((cfg->vector == vector) && cpumask_equal(&cfg->domain, &domain)) in __bind_irq_vector()
140 if (cfg->vector != IRQ_VECTOR_UNASSIGNED) in __bind_irq_vector()
144 cfg->vector = vector; in __bind_irq_vector()
145 cfg->domain = domain; in __bind_irq_vector()
166 struct irq_cfg *cfg = &irq_cfg[irq]; in __clear_irq_vector() local
169 BUG_ON(cfg->vector == IRQ_VECTOR_UNASSIGNED); in __clear_irq_vector()
170 vector = cfg->vector; in __clear_irq_vector()
171 domain = cfg->domain; in __clear_irq_vector()
172 for_each_cpu_and(cpu, &cfg->domain, cpu_online_mask) in __clear_irq_vector()
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/arch/x86/kernel/
Dhpet.c235 u32 cfg = hpet_readl(HPET_CFG); in hpet_stop_counter() local
236 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
237 hpet_writel(cfg, HPET_CFG); in hpet_stop_counter()
248 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_start_counter() local
249 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
250 hpet_writel(cfg, HPET_CFG); in hpet_start_counter()
273 unsigned int cfg = hpet_readl(HPET_CFG); in hpet_enable_legacy_int() local
275 cfg |= HPET_CFG_LEGACY; in hpet_enable_legacy_int()
276 hpet_writel(cfg, HPET_CFG); in hpet_enable_legacy_int()
298 unsigned int cfg, cmp, now; in hpet_set_periodic() local
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/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_sw_cfg_defs.h90 unsigned int cfg : 2; member
98 unsigned int cfg : 2; member
106 unsigned int cfg : 2; member
114 unsigned int cfg : 2; member
122 unsigned int cfg : 2; member
130 unsigned int cfg : 2; member
138 unsigned int cfg : 2; member
146 unsigned int cfg : 2; member
154 unsigned int cfg : 2; member
162 unsigned int cfg : 2; member
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/arch/arm/plat-orion/include/plat/
Daddr-map.h24 int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg,
28 void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg,
44 void __init orion_config_wins(struct orion_addr_map_cfg *cfg,
47 void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
52 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_sw_cfg_defs.h87 unsigned int cfg : 2; member
95 unsigned int cfg : 2; member
103 unsigned int cfg : 2; member
111 unsigned int cfg : 2; member
119 unsigned int cfg : 2; member
127 unsigned int cfg : 2; member
135 unsigned int cfg : 2; member
143 unsigned int cfg : 2; member
151 unsigned int cfg : 2; member
159 unsigned int cfg : 2; member
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/arch/x86/kernel/apic/
Dipi.c30 unsigned int cfg; in __default_send_IPI_shortcut() local
40 cfg = __prepare_ICR(shortcut, vector, dest); in __default_send_IPI_shortcut()
45 native_apic_mem_write(APIC_ICR, cfg); in __default_send_IPI_shortcut()
54 unsigned long cfg; in __default_send_IPI_dest_field() local
67 cfg = __prepare_ICR2(mask); in __default_send_IPI_dest_field()
68 native_apic_mem_write(APIC_ICR2, cfg); in __default_send_IPI_dest_field()
73 cfg = __prepare_ICR(0, vector, dest); in __default_send_IPI_dest_field()
78 native_apic_mem_write(APIC_ICR, cfg); in __default_send_IPI_dest_field()
Dvector.c26 struct irq_cfg cfg; member
69 return data ? &data->cfg : NULL; in irqd_cfg()
162 vector = d->cfg.vector; in __assign_irq_vector()
190 if (d->cfg.vector) in __assign_irq_vector()
218 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0; in __assign_irq_vector()
219 d->cfg.vector = vector; in __assign_irq_vector()
232 &d->cfg.dest_apicid)); in __assign_irq_vector()
267 if (!data->cfg.vector) in clear_irq_vector()
270 vector = data->cfg.vector; in clear_irq_vector()
274 data->cfg.vector = 0; in clear_irq_vector()
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/arch/powerpc/platforms/cell/
Dspider-pic.c85 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq() local
87 out_be32(cfg, in_be32(cfg) | 0x30000000u); in spider_unmask_irq()
93 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq() local
95 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_mask_irq()
121 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type() local
155 old_mask = in_be32(cfg) & 0x30000000u; in spider_set_irq_type()
156 out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) | in spider_set_irq_type()
158 out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff)); in spider_set_irq_type()
309 void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i; in spider_init_one() local
310 out_be32(cfg, in_be32(cfg) & ~0x30000000u); in spider_init_one()
/arch/arc/include/asm/
Dsetup.h40 #define IS_USED_CFG(cfg) IS_USED_RUN(IS_ENABLED(cfg)) argument
41 #define IS_AVAIL2(v, s, cfg) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg)) argument
/arch/sparc/include/asm/
Dsbi.h97 int cfg; in get_sbi_ctl() local
100 "=r" (cfg) : in get_sbi_ctl()
103 return cfg; in get_sbi_ctl()
106 static inline void set_sbi_ctl(int devid, int cfgno, int cfg) in set_sbi_ctl() argument
109 "r" (cfg), in set_sbi_ctl()
/arch/mips/include/asm/
Dmaar.h107 static inline unsigned maar_config(const struct maar_config *cfg, in maar_config() argument
113 write_maar_pair(i, cfg[i].lower, cfg[i].upper, cfg[i].attrs); in maar_config()

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