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Searched refs:csr_out32 (Results 1 – 3 of 3) sorted by relevance

/arch/mips/sibyte/common/
Dbus_watcher.c186 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bw_int()
187 csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bw_int()
193 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bw_int()
194 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bw_int()
206 csr_out32(0, IOADDR(A_BUS_L2_ERRORS)); in sibyte_bw_int()
212 csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS)); in sibyte_bw_int()
243 csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE | in sibyte_bus_watcher()
246 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bus_watcher()
247 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG)); in sibyte_bus_watcher()
/arch/mips/mm/
Dcerr-sb1.c185 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); in sb1_cache_error()
/arch/mips/include/asm/
Dio.h615 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) macro