| /arch/m32r/include/asm/ |
| D | cacheflush.h | 21 #define flush_icache_range(start, end) _flush_cache_copyback_all() macro
27 #define flush_icache_range(start, end) smp_flush_cache_all() macro
42 #define flush_icache_range(start, end) _flush_cache_all() macro
56 #define flush_icache_range(start, end) do { } while (0) macro
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| /arch/ia64/sn/kernel/sn2/ |
| D | cache.c | 32 flush_icache_range(addr, addr + bytes); in sn_flush_all_caches()
38 flush_icache_range(addr, addr + bytes); in sn_flush_all_caches()
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| /arch/arc/kernel/ |
| D | kprobes.c | 44 flush_icache_range((unsigned long)p->addr, in arch_arm_kprobe()
52 flush_icache_range((unsigned long)p->addr, in arch_disarm_kprobe()
64 flush_icache_range((unsigned long)p->ainsn.t1_addr, in arch_remove_kprobe()
74 flush_icache_range((unsigned long)p->ainsn.t2_addr, in arch_remove_kprobe()
108 flush_icache_range((unsigned long)p->ainsn.t1_addr, in resume_execution()
118 flush_icache_range((unsigned long)p->ainsn.t2_addr, in resume_execution()
141 flush_icache_range((unsigned long)p->addr, in setup_singlestep()
181 flush_icache_range((unsigned long)p->ainsn.t1_addr, in setup_singlestep()
190 flush_icache_range((unsigned long)p->ainsn.t2_addr, in setup_singlestep()
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| /arch/hexagon/mm/ |
| D | cache.c | 48 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() function
71 EXPORT_SYMBOL(flush_icache_range);
136 flush_icache_range((unsigned long) dst, in copy_to_user_page()
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| /arch/tile/include/asm/ |
| D | cacheflush.h | 52 extern void flush_icache_range(unsigned long start, unsigned long end);
54 #define flush_icache_range __flush_icache_range macro
70 flush_icache_range((unsigned long) dst, in copy_to_user_page()
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| /arch/ia64/lib/ |
| D | flush.S | 25 GLOBAL_ENTRY(flush_icache_range)
63 END(flush_icache_range)
64 EXPORT_SYMBOL_GPL(flush_icache_range)
|
| /arch/xtensa/include/asm/ |
| D | cacheflush.h | 100 void flush_icache_range(unsigned long start, unsigned long end);
106 #define flush_icache_range local_flush_icache_range macro
142 #define flush_icache_range local_flush_icache_range macro
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| /arch/mips/pistachio/ |
| D | init.c | 95 flush_icache_range((unsigned long)base, in mips_nmi_setup()
108 flush_icache_range((unsigned long)base, in mips_ejtag_setup()
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| /arch/c6x/include/asm/ |
| D | cacheflush.h | 40 #define flush_icache_range(s, e) \ macro
59 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
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| /arch/ia64/include/asm/ |
| D | cacheflush.h | 38 extern void flush_icache_range (unsigned long start, unsigned long end);
45 flush_icache_range(_addr, _addr + (len)); \
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| /arch/mn10300/include/asm/ |
| D | cacheflush.h | 136 extern void flush_icache_range(unsigned long start, unsigned long end);
143 extern void flush_icache_range(unsigned long start, unsigned long end);
145 #define flush_icache_range(start, end) do {} while (0) macro
151 flush_icache_range(adr, adr + len)
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| /arch/score/mm/ |
| D | cache.c | 206 flush_icache_range(start, tmpend); in flush_cache_range()
220 flush_icache_range(kaddr, kaddr + PAGE_SIZE); in flush_cache_page()
265 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() function
281 EXPORT_SYMBOL(flush_icache_range);
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| /arch/score/include/asm/ |
| D | cacheflush.h | 16 extern void flush_icache_range(unsigned long start, unsigned long end);
34 flush_icache_range((unsigned long) v, in flush_icache_page()
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| /arch/arm64/mm/ |
| D | flush.c | 36 flush_icache_range(addr, addr + len); in sync_icache_aliases()
85 EXPORT_SYMBOL(flush_icache_range);
|
| /arch/alpha/include/asm/ |
| D | cacheflush.h | 33 #define flush_icache_range(start, end) imb() macro
35 #define flush_icache_range(start, end) smp_imb() macro
|
| /arch/m68k/mm/ |
| D | cache.c | 76 void flush_icache_range(unsigned long address, unsigned long endaddr) in flush_icache_range() function
107 EXPORT_SYMBOL(flush_icache_range);
|
| /arch/mn10300/mm/ |
| D | cache-inv-icache.c | 84 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() function
129 EXPORT_SYMBOL(flush_icache_range);
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| D | cache-flush-icache.c | 108 void flush_icache_range(unsigned long start, unsigned long end) in flush_icache_range() function
155 EXPORT_SYMBOL(flush_icache_range);
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| /arch/arm/kernel/ |
| D | fiq.c | 101 flush_icache_range((unsigned long)base + offset, offset + in set_fiq_handler()
103 flush_icache_range(0xffff0000 + offset, 0xffff0000 + offset + length); in set_fiq_handler()
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| /arch/mn10300/kernel/ |
| D | switch_to.S | 105 calls flush_icache_range
119 calls flush_icache_range
152 calls flush_icache_range
167 calls flush_icache_range
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| /arch/blackfin/include/asm/ |
| D | cacheflush.h | 40 static inline void flush_icache_range(unsigned start, unsigned end) in flush_icache_range() function
76 flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
|
| /arch/microblaze/include/asm/ |
| D | cacheflush.h | 60 #define flush_icache_range(start, end) mbc->iflr(start, end); macro
98 flush_icache_range((unsigned) (start), (unsigned) (start) + (len)); \
|
| /arch/arm/include/asm/ |
| D | fncpy.h | 85 flush_icache_range((unsigned long)(dest_buf), \
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| /arch/mips/loongson64/common/ |
| D | init.c | 29 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_nmi_setup()
|
| /arch/mips/kernel/ |
| D | ftrace.c | 90 flush_icache_range(ip, ip + 8); in ftrace_modify_code()
115 flush_icache_range(ip, ip + 8); in ftrace_modify_code_2()
139 flush_icache_range(ip, ip + 8); in ftrace_modify_code_2r()
|