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/arch/arm/vfp/
Dvfpinstr.h13 #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000) argument
14 #define INST_CPRT(inst) ((inst) & (1 << 4)) argument
15 #define INST_CPRT_L(inst) ((inst) & (1 << 20)) argument
16 #define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12) argument
17 #define INST_CPRT_OP(inst) (((inst) >> 21) & 7) argument
18 #define INST_CPNUM(inst) ((inst) & 0xf00) argument
33 #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) argument
52 #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) argument
54 #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) argument
55 #define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) argument
[all …]
/arch/powerpc/include/asm/
Ddisassemble.h25 static inline unsigned int get_op(u32 inst) in get_op() argument
27 return inst >> 26; in get_op()
30 static inline unsigned int get_xop(u32 inst) in get_xop() argument
32 return (inst >> 1) & 0x3ff; in get_xop()
35 static inline unsigned int get_sprn(u32 inst) in get_sprn() argument
37 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_sprn()
40 static inline unsigned int get_dcrn(u32 inst) in get_dcrn() argument
42 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_dcrn()
45 static inline unsigned int get_tmrn(u32 inst) in get_tmrn() argument
47 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); in get_tmrn()
[all …]
/arch/arm64/kernel/
Dkuser32.S38 .inst 0xe92d00f0 // push {r4, r5, r6, r7}
39 .inst 0xe1c040d0 // ldrd r4, r5, [r0]
40 .inst 0xe1c160d0 // ldrd r6, r7, [r1]
41 .inst 0xe1b20f9f // 1: ldrexd r0, r1, [r2]
42 .inst 0xe0303004 // eors r3, r0, r4
43 .inst 0x00313005 // eoreqs r3, r1, r5
44 .inst 0x01a23e96 // stlexdeq r3, r6, [r2]
45 .inst 0x03330001 // teqeq r3, #1
46 .inst 0x0afffff9 // beq 1b
47 .inst 0xf57ff05b // dmb ish
[all …]
/arch/cris/include/arch-v32/arch/hwregs/
Ddma.h76 #define DMA_ENABLE( inst ) \ argument
77 do { reg_dma_rw_cfg e = REG_RD( dma, inst, rw_cfg );\
79 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
82 #define DMA_RESET( inst ) \ argument
83 do { reg_dma_rw_cfg r = REG_RD( dma, inst, rw_cfg );\
85 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
88 #define DMA_STOP( inst ) \ argument
89 do { reg_dma_rw_cfg s = REG_RD( dma, inst, rw_cfg );\
91 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
94 #define DMA_CONTINUE( inst ) \ argument
[all …]
Dirq_nmi_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dstrcop_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dmarb_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dconfig_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Drt_trace_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
/arch/powerpc/kernel/
Dkvm.c81 static inline void kvm_patch_ins(u32 *inst, u32 new_inst) in kvm_patch_ins() argument
83 *inst = new_inst; in kvm_patch_ins()
84 flush_icache_range((ulong)inst, (ulong)inst + 4); in kvm_patch_ins()
87 static void kvm_patch_ins_ll(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ll() argument
90 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
92 kvm_patch_ins(inst, KVM_INST_LWZ | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ll()
96 static void kvm_patch_ins_ld(u32 *inst, long addr, u32 rt) in kvm_patch_ins_ld() argument
99 kvm_patch_ins(inst, KVM_INST_LD | rt | (addr & 0x0000fffc)); in kvm_patch_ins_ld()
101 kvm_patch_ins(inst, KVM_INST_LWZ | rt | ((addr + 4) & 0x0000fffc)); in kvm_patch_ins_ld()
105 static void kvm_patch_ins_lwz(u32 *inst, long addr, u32 rt) in kvm_patch_ins_lwz() argument
[all …]
/arch/arm/mach-omap2/
Dcm33xx.c51 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx) in am33xx_cm_read_reg() argument
53 return readl_relaxed(cm_base.va + inst + idx); in am33xx_cm_read_reg()
57 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx) in am33xx_cm_write_reg() argument
59 writel_relaxed(val, cm_base.va + inst + idx); in am33xx_cm_write_reg()
63 static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) in am33xx_cm_rmw_reg_bits() argument
67 v = am33xx_cm_read_reg(inst, idx); in am33xx_cm_rmw_reg_bits()
70 am33xx_cm_write_reg(v, inst, idx); in am33xx_cm_rmw_reg_bits()
83 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
85 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); in _clkctrl_idlest()
99 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
[all …]
Dprminst44xx.c61 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx) in omap4_prminst_read_inst_reg() argument
66 return readl_relaxed(_prm_bases[part].va + inst + idx); in omap4_prminst_read_inst_reg()
70 void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx) in omap4_prminst_write_inst_reg() argument
75 writel_relaxed(val, _prm_bases[part].va + inst + idx); in omap4_prminst_write_inst_reg()
79 u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, in omap4_prminst_rmw_inst_reg_bits() argument
84 v = omap4_prminst_read_inst_reg(part, inst, idx); in omap4_prminst_rmw_inst_reg_bits()
87 omap4_prminst_write_inst_reg(v, part, inst, idx); in omap4_prminst_rmw_inst_reg_bits()
102 int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst, in omap4_prminst_is_hardreset_asserted() argument
107 v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs); in omap4_prminst_is_hardreset_asserted()
126 int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, in omap4_prminst_assert_hardreset() argument
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h16 #define REG_RD( scope, inst, reg ) \ argument
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \ argument
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
42 #define REG_RD_INT( scope, inst, reg ) \ argument
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Diop_sap_in_defs.h16 #define REG_RD( scope, inst, reg ) \ argument
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \ argument
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
42 #define REG_RD_INT( scope, inst, reg ) \ argument
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Diop_scrc_in_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Diop_scrc_out_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Diop_trigger_grp_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dstrmux_defs.h16 #define REG_RD( scope, inst, reg ) \ argument
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \ argument
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
42 #define REG_RD_INT( scope, inst, reg ) \ argument
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dmarb_bar_defs.h16 #define REG_RD( scope, inst, reg ) \ argument
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \ argument
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
42 #define REG_RD_INT( scope, inst, reg ) \ argument
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dl2cache_defs.h16 #define REG_RD( scope, inst, reg ) \ argument
18 (inst) + REG_RD_ADDR_##scope##_##reg )
22 #define REG_WR( scope, inst, reg, val ) \ argument
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
35 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
42 #define REG_RD_INT( scope, inst, reg ) \ argument
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dstrmux_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dmarb_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
Dconfig_defs.h19 #define REG_RD( scope, inst, reg ) \ argument
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \ argument
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
45 #define REG_RD_INT( scope, inst, reg ) \ argument
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
[all …]
/arch/x86/crypto/
Dfpu.c86 struct skcipher_instance *inst = skcipher_alg_instance(tfm); in crypto_fpu_init_tfm() local
91 spawn = skcipher_instance_ctx(inst); in crypto_fpu_init_tfm()
108 static void crypto_fpu_free(struct skcipher_instance *inst) in crypto_fpu_free() argument
110 crypto_drop_skcipher(skcipher_instance_ctx(inst)); in crypto_fpu_free()
111 kfree(inst); in crypto_fpu_free()
117 struct skcipher_instance *inst; in crypto_fpu_create() local
138 inst = kzalloc(sizeof(*inst) + sizeof(*spawn), GFP_KERNEL); in crypto_fpu_create()
139 if (!inst) in crypto_fpu_create()
142 spawn = skcipher_instance_ctx(inst); in crypto_fpu_create()
144 crypto_set_skcipher_spawn(spawn, skcipher_crypto_instance(inst)); in crypto_fpu_create()
[all …]

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