| /arch/mips/include/asm/ |
| D | mips-gic.h | 53 static inline void __iomem *addr_gic_##name(unsigned int intr) \
55 return mips_gic_base + (off) + (intr * (stride)); \
58 static inline unsigned int read_gic_##name(unsigned int intr) \
61 return __raw_readl(addr_gic_##name(intr)); \
68 static inline void write_gic_##name(unsigned int intr, \
72 __raw_writel(val, addr_gic_##name(intr)); \
96 static inline unsigned int read_gic_##name(unsigned int intr) \
102 addr += (intr / 64) * sizeof(uint64_t); \
103 val = __raw_readq(addr) >> intr % 64; \
105 addr += (intr / 32) * sizeof(uint32_t); \
[all …]
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_pic.c | 133 static struct mpc52xx_intr __iomem *intr; variable
161 io_be_clrbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_mask()
167 io_be_setbit(&intr->ctrl, 11 - l2irq); in mpc52xx_extirq_unmask()
173 io_be_setbit(&intr->ctrl, 27-l2irq); in mpc52xx_extirq_ack()
194 ctrl_reg = in_be32(&intr->ctrl); in mpc52xx_extirq_set_type()
197 out_be32(&intr->ctrl, ctrl_reg); in mpc52xx_extirq_set_type()
223 io_be_setbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_mask()
229 io_be_clrbit(&intr->main_mask, 16 - l2irq); in mpc52xx_main_unmask()
246 io_be_setbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_mask()
252 io_be_clrbit(&intr->per_mask, 31 - l2irq); in mpc52xx_periph_unmask()
[all …]
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| D | mpc52xx_pm.c | 20 static struct mpc52xx_intr __iomem *intr; variable
89 intr = mbar + 0x500; in mpc52xx_pm_prepare()
123 intr_main_mask = in_be32(&intr->main_mask); in mpc52xx_pm_enter()
124 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); in mpc52xx_pm_enter()
157 mpc52xx_deep_sleep(sram, sdram, cdm, intr); in mpc52xx_pm_enter()
176 out_be32(&intr->main_mask, intr_main_mask); in mpc52xx_pm_enter()
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| /arch/x86/platform/intel-mid/device_libs/ |
| D | platform_tca6416.c | 26 int gpio_base, intr; in tca6416_platform_data() local
35 intr = get_gpio_by_name(intr_pin_name); in tca6416_platform_data()
40 if (intr >= 0) { in tca6416_platform_data()
41 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in tca6416_platform_data()
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| D | platform_mpu3050.c | 20 int intr = get_gpio_by_name("mpu3050_int"); in mpu3050_platform_data() local
22 if (intr < 0) in mpu3050_platform_data()
25 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in mpu3050_platform_data()
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| D | platform_lis331.c | 21 int intr = get_gpio_by_name("accel_int"); in lis331dl_platform_data() local
24 if (intr < 0) in lis331dl_platform_data()
29 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in lis331dl_platform_data()
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| D | platform_emc1403.c | 22 int intr = get_gpio_by_name("thermal_int"); in emc1403_platform_data() local
25 if (intr < 0) in emc1403_platform_data()
30 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in emc1403_platform_data()
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| D | platform_max7315.c | 27 int gpio_base, intr; in max7315_platform_data() local
51 intr = get_gpio_by_name(intr_pin_name); in max7315_platform_data()
56 if (intr != -1) { in max7315_platform_data()
57 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in max7315_platform_data()
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| D | platform_pcal9555a.c | 35 int gpio_base, intr; in pcal9555a_platform_data() local
41 intr = get_gpio_by_name(intr_pin_name); in pcal9555a_platform_data()
56 if (intr >= 0) { in pcal9555a_platform_data()
57 i2c_info->irq = intr + INTEL_MID_IRQ_OFFSET; in pcal9555a_platform_data()
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| /arch/ia64/hp/sim/ |
| D | hpsim_irq.c | 51 static void hpsim_connect_irq(int intr, int irq) in hpsim_connect_irq() argument
53 ia64_ssc(intr, irq, 0, 0, SSC_CONNECT_INTERRUPT); in hpsim_connect_irq()
56 int hpsim_get_irq(int intr) in hpsim_get_irq() argument
63 hpsim_connect_irq(intr, irq); in hpsim_get_irq()
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| /arch/mips/pci/ |
| D | ops-gt64xxx_pci0.c | 46 u32 intr; in gt64xxx_pci0_pcibios_config_access() local
83 intr = GT_READ(GT_INTRCAUSE_OFS); in gt64xxx_pci0_pcibios_config_access()
85 if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { in gt64xxx_pci0_pcibios_config_access()
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| D | ops-msc.c | 50 u32 intr; in msc_pcibios_config_access() local
69 MSC_READ(MSC01_PCI_INTSTAT, intr); in msc_pcibios_config_access()
70 if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) { in msc_pcibios_config_access()
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| D | ops-pmcmsp.c | 124 int intr; in gen_pci_cfg_wr_show() local
157 intr = preg->if_status; in gen_pci_cfg_wr_show()
369 unsigned long intr; in msp_pcibios_config_access() local
442 intr = preg->if_status; in msp_pcibios_config_access()
448 if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) { in msp_pcibios_config_access()
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-ciu3-defs.h | 98 uint64_t intr : 1; member
100 uint64_t intr : 1;
119 uint64_t intr : 1; member
121 uint64_t intr : 1;
151 uint64_t intr : 1; member
157 uint64_t intr : 1;
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| /arch/cris/include/arch-v32/arch/hwregs/ |
| D | dma.h | 23 unsigned intr : 1; member
41 unsigned intr : 1; member
63 unsigned intr : 1; member
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| D | dma_defs.h | 108 unsigned int intr : 1; member
159 unsigned int intr : 1; member
259 unsigned int intr : 1; member
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| /arch/mips/kvm/ |
| D | interrupt.c | 57 int intr = (int)irq->irq; in kvm_mips_queue_io_int_cb() local
64 switch (intr) { in kvm_mips_queue_io_int_cb()
90 int intr = (int)irq->irq; in kvm_mips_dequeue_io_int_cb() local
92 switch (intr) { in kvm_mips_dequeue_io_int_cb()
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| /arch/arm/mach-pxa/ |
| D | pxa27x-udc.h | 41 #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) argument
50 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) argument
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| D | regs-u2d.h | 45 #define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) argument
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| /arch/tile/include/hv/ |
| D | drv_pcie_rc_intf.h | 34 int intr; /**< interrupt number used for downcall */ member
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| /arch/sparc/kernel/ |
| D | prom_32.c | 139 unsigned int *intr, *device, *vendor, reg0; in ambapp_path_component() local
157 intr = &interrupt; /* IRQ0 does not exist */ in ambapp_path_component()
159 intr = prop->value; in ambapp_path_component()
172 *intr, reg0); in ambapp_path_component()
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| D | of_device_32.c | 343 const struct linux_prom_irqs *intr; in scan_one_device() local
355 intr = of_get_property(dp, "intr", &len); in scan_one_device()
356 if (intr) { in scan_one_device()
360 sparc_config.build_device_irq(op, intr[i].pri); in scan_one_device()
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| /arch/ia64/include/asm/ |
| D | hpsim.h | 14 extern int hpsim_get_irq(int intr);
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| /arch/cris/arch-v32/kernel/ |
| D | time.c | 212 reg_timer_r_masked_intr intr; in crisv32_timer_interrupt() local
214 intr = REG_RD(timer, timer_base, r_masked_intr); in crisv32_timer_interrupt()
215 if (!intr.tmr0) in crisv32_timer_interrupt()
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| /arch/ia64/include/asm/sn/ |
| D | sn_sal.h | 409 ia64_sn_console_intr_enable(u64 intr) in ia64_sn_console_intr_enable() argument
418 intr, SAL_CONSOLE_INTR_ON, in ia64_sn_console_intr_enable()
426 ia64_sn_console_intr_disable(u64 intr) in ia64_sn_console_intr_disable() argument
435 intr, SAL_CONSOLE_INTR_OFF, in ia64_sn_console_intr_disable()
877 ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr) in ia64_sn_irtr_intr_enable() argument
881 (u64) nasid, (u64) subch, intr, 0, 0, 0); in ia64_sn_irtr_intr_enable()
890 ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr) in ia64_sn_irtr_intr_disable() argument
894 (u64) nasid, (u64) subch, intr, 0, 0, 0); in ia64_sn_irtr_intr_disable()
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