| /arch/mn10300/mm/ |
| D | Makefile | 9 cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
10 cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
12 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
13 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
18 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
22 cache-dbg-inv-by-tag.o cache-dbg-inv.o
24 cache-dbg-inv-by-reg.o cache-dbg-inv.o
|
| /arch/cris/arch-v10/mm/ |
| D | fault.c | 47 int acc, inv; in handle_mmu_bus_fault() local
64 inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause); in handle_mmu_bus_fault()
72 regs->irp, address, miss, inv, we, acc, index, page_id)); in handle_mmu_bus_fault()
|
| /arch/arm/mm/ |
| D | proc-feroceon.S | 265 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
266 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
311 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
312 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
374 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
375 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
|
| /arch/mips/boot/dts/brcm/ |
| D | bcm63268-comtrend-vr-3032u.dts | 25 brcm,serial-shift-inv;
|
| /arch/cris/include/arch-v32/arch/hwregs/iop/ |
| D | iop_timer_grp_defs.h | 122 unsigned int inv : 1; member
|
| /arch/x86/events/intel/ |
| D | p6.c | 188 PMU_FORMAT_ATTR(inv, "config:23" );
|
| D | knc.c | 278 PMU_FORMAT_ATTR(inv, "config:23" );
|
| D | core.c | 2923 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
2951 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
2975 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3310 PMU_FORMAT_ATTR(inv, "config:23" );
4106 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
4109 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
4234 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
4237 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
4273 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
4276 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
[all …]
|
| D | uncore_snb.c | 99 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
|
| D | uncore_nhmex.c | 194 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| D | uncore_snbep.c | 336 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
|
| /arch/cris/arch-v32/mm/ |
| D | init.c | 54 REG_STATE(mmu, rw_mm_cfg, inv, on) | in cris_mmu_init()
|
| /arch/cris/arch-v32/kernel/ |
| D | head.S | 96 | REG_STATE(mmu, rw_mm_cfg, inv, on) \
117 | REG_STATE(mmu, rw_mm_cfg, inv, on) \
|
| /arch/x86/events/amd/ |
| D | core.c | 708 PMU_FORMAT_ATTR(inv, "config:23" );
|
| /arch/x86/events/ |
| D | perf_event.h | 492 inv:1, member
|
| D | core.c | 1708 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); in x86_event_sysfs_show() local
1729 if (inv) in x86_event_sysfs_show()
|
| /arch/arm/crypto/ |
| D | aes-neonbs-core.S | 305 t0, t1, t2, t3, t4, t5, t6, t7, inv argument
344 .ifb \inv
|
| /arch/arm64/crypto/ |
| D | aes-neonbs-core.S | 253 t0, t1, t2, t3, t4, t5, t6, t7, inv argument
292 .ifb \inv
|
| /arch/arm/boot/dts/ |
| D | omap3-n900.dts | 785 clock-inv = <0>;
|