| /arch/mips/math-emu/ |
| D | cp1emu.c | 853 mips_instruction ir) in cop1_cfc() argument
858 switch (MIPSInst_RD(ir)) { in cop1_cfc()
862 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
872 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
880 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
891 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
902 if (MIPSInst_RT(ir)) in cop1_cfc()
903 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
910 mips_instruction ir) in cop1_ctc() argument
916 if (MIPSInst_RT(ir) == 0) in cop1_ctc()
[all …]
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| D | dsemul.c | 212 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, in mips_dsemul() argument
222 if (ir == 0) in mips_dsemul()
227 union mips_instruction insn = { .word = ir }; in mips_dsemul()
230 if ((ir >> 16) == MM_NOP16) in mips_dsemul()
261 .halfword = { ir >> 16, ir } in mips_dsemul()
270 fr.emul = ir; in mips_dsemul()
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| /arch/mips/kernel/ |
| D | mips-r2-to-r6-emul.c | 78 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) in mipsr6_emul() argument
80 switch (MIPSInst_OPCODE(ir)) { in mipsr6_emul()
82 if (MIPSInst_RT(ir)) in mipsr6_emul()
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
85 (s32)MIPSInst_SIMM(ir); in mipsr6_emul()
91 if (MIPSInst_RT(ir)) in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
94 (s64)MIPSInst_SIMM(ir); in mipsr6_emul()
[all …]
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| /arch/parisc/math-emu/ |
| D | fpudispatch.c | 195 fpudispatch(u_int ir, u_int excp_code, u_int holder, u_int fpregs[]) in fpudispatch() argument
207 class = get_class(ir); in fpudispatch()
210 subop = get_subop1_PA2_0(ir); in fpudispatch()
212 subop = get_subop1_PA1_1(ir); in fpudispatch()
215 subop = get_subop(ir); in fpudispatch()
222 return(decode_0c(ir,class,subop,fpregs)); in fpudispatch()
224 return(decode_0e(ir,class,subop,fpregs)); in fpudispatch()
226 return(decode_06(ir,fpregs)); in fpudispatch()
228 return(decode_26(ir,fpregs)); in fpudispatch()
230 return(decode_2e(ir,fpregs)); in fpudispatch()
[all …]
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| /arch/arm/boot/dts/ |
| D | rk3288-firefly.dts | 51 &ir {
62 ir {
63 ir_int: ir-int {
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| D | rk3288-firefly-beta.dts | 51 &ir {
62 ir {
63 ir_int: ir-int {
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| D | rk3288-rock2-square.dts | 68 ir: ir-receiver { label
69 compatible = "gpio-ir-receiver";
217 ir {
218 ir_int: ir-int {
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| D | dove-cubox.dts | 60 ir_recv: ir-receiver {
61 compatible = "gpio-ir-receiver";
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| D | rk3288-r89.dts | 80 ir: ir-receiver { label
81 compatible = "gpio-ir-receiver";
319 ir {
320 ir_int: ir-int {
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| D | rk3066a-rayeager.dts | 56 ir: ir-receiver { label
57 compatible = "gpio-ir-receiver";
373 ir {
374 ir_int: ir-int {
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| D | rk3288-popmetal.dts | 80 ir: ir-receiver { label
81 compatible = "gpio-ir-receiver";
466 ir {
467 ir_int: ir-int {
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| D | rk3188-radxarock.dts | 107 ir_recv: gpio-ir-receiver {
108 compatible = "gpio-ir-receiver";
347 ir-receiver {
348 ir_recv_pin: ir-recv-pin {
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| D | imx6qdl-cubox-i.dtsi | 47 ir_recv: ir-receiver {
48 compatible = "gpio-ir-receiver";
170 pinctrl_cubox_i_ir: cubox-i-ir {
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| D | rk3288-firefly-reload.dts | 77 ir-receiver {
78 compatible = "gpio-ir-receiver";
334 ir {
335 ir_int: ir-int {
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| D | sunxi-h3-h5.dtsi | 591 ir: ir@01f02000 { label
592 compatible = "allwinner,sun5i-a13-ir";
594 clock-names = "apb", "ir";
612 ir_pins_a: ir@0 {
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| /arch/mips/include/asm/ |
| D | dsemul.h | 41 extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir,
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| D | msa.h | 229 __BUILD_MSA_CTL_REG(ir, 0)
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| /arch/s390/include/asm/ |
| D | ap.h | 99 unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */ member
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| /arch/arm64/boot/dts/rockchip/ |
| D | rk3368-geekbox.dts | 67 ir: ir-receiver { label
68 compatible = "gpio-ir-receiver";
272 ir {
273 ir_int: ir-int {
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| D | rk3368-r88.dts | 91 ir: ir-receiver { label
92 compatible = "gpio-ir-receiver";
299 ir {
300 ir_int: ir-int {
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| /arch/arm64/net/ |
| D | bpf_jit.h | 122 #define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED) argument
124 #define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED) argument
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| /arch/powerpc/platforms/4xx/ |
| D | gpio.c | 46 __be32 ir; member
75 return !!(in_be32(®s->ir) & GPIO_MASK(gpio)); in ppc4xx_gpio_get()
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| /arch/mips/boot/dts/img/ |
| D | pistachio.dtsi | 638 ir_pin: ir-pin {
639 ir-data {
641 function = "ir";
758 ir: ir@18102200 { label
759 compatible = "img,ir-rev1";
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| /arch/arm64/boot/dts/hisilicon/ |
| D | hi3798cv200.dtsi | 403 ir: ir@8001000 { label
404 compatible = "hisilicon,hix5hd2-ir";
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| D | hi3798cv200-poplar.dts | 145 &ir {
|