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Searched refs:mask0 (Results 1 – 9 of 9) sorted by relevance

/arch/parisc/kernel/
Dsys_parisc32.c28 compat_uint_t mask0, compat_uint_t mask1, compat_int_t dfd, in sys32_fanotify_mark() argument
32 ((__u64)mask1 << 32) | mask0, in sys32_fanotify_mark()
/arch/mips/sgi-ip27/
Dip27-nmi.c133 hubreg_t mask0, mask1, pend0, pend1; in nmi_dump_hub_irq() local
136 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A); in nmi_dump_hub_irq()
139 mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B); in nmi_dump_hub_irq()
146 printk("PI_INT_MASK0: %16Lx PI_INT_MASK1: %16Lx\n", mask0, mask1); in nmi_dump_hub_irq()
Dip27-irq.c88 hubreg_t pend0, mask0; in ip27_do_irq_mask0() local
95 mask0 = LOCAL_HUB_L(pi_int_mask0); in ip27_do_irq_mask0()
97 pend0 &= mask0; /* Pick intrs we should look at */ in ip27_do_irq_mask0()
/arch/alpha/kernel/
Dsys_titan.c70 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
74 mask0 = mask & titan_cpu_irq_affinity[0]; in titan_update_irq_hw()
79 if (bcpu == 0) mask0 |= isa_enable; in titan_update_irq_hw()
93 *dim0 = mask0; in titan_update_irq_hw()
Dsys_dp264.c56 unsigned long mask0, mask1, mask2, mask3, dummy; in tsunami_update_irq_hw() local
59 mask0 = mask & cpu_irq_affinity[0]; in tsunami_update_irq_hw()
64 if (bcpu == 0) mask0 |= isa_enable; in tsunami_update_irq_hw()
78 *dim0 = mask0; in tsunami_update_irq_hw()
/arch/frv/kernel/
Dgdb-stub.c851 unsigned long mask0, mask1; in gdbstub_set_breakpoint() member
962 __debug_regs->dbmr[0][0] = dbmr.mask0; in gdbstub_set_breakpoint()
972 : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1)); in gdbstub_set_breakpoint()
982 __debug_regs->dbmr[1][0] = dbmr.mask0; in gdbstub_set_breakpoint()
992 : : "r"(addr), "r"(dbmr.mask0), "r"(dbmr.mask1)); in gdbstub_set_breakpoint()
1015 unsigned long mask0, mask1; in gdbstub_clear_breakpoint() member
1104 __get_dbmr0(0) != dbmr.mask0 || in gdbstub_clear_breakpoint()
1129 __get_dbmr0(1) != dbmr.mask0 || in gdbstub_clear_breakpoint()
/arch/xtensa/lib/
Dstrnlen_user.S44 # a5/ mask0
Dstrncpy_user.S47 # a5/ mask0
/arch/x86/events/intel/
Duncore_snbep.c397 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");