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Searched refs:mtctl (Results 1 – 15 of 15) sorted by relevance

/arch/parisc/kernel/
Dhead.S74 mtctl %r4,%cr24 /* Initialize kernel root pointer */
75 mtctl %r4,%cr25 /* Initialize user root pointer */
127 mtctl %r6,%cr30
215 mtctl %r6,%cr30 /* restore task thread info */
231 mtctl %r0,%cr8
232 mtctl %r0,%cr9
233 mtctl %r0,%cr12
234 mtctl %r0,%cr13
247 mtctl %r10,%cr11
262 mtctl %r10,%cr14
[all …]
Dreal2.S126 # define POP_CR(r, where) LDREG,mb -REG_SZ(where), %r1 ! mtctl %r1, r
176 mtctl %r0, %cr17 /* Clear IIASQ tail */
177 mtctl %r0, %cr17 /* Clear IIASQ head */
178 mtctl %r1, %cr18 /* IIAOQ head */
180 mtctl %r1, %cr18 /* IIAOQ tail */
182 mtctl %r1, %cr22
213 mtctl %r0, %cr17 /* Clear IIASQ tail */
214 mtctl %r0, %cr17 /* Clear IIASQ head */
215 mtctl %r1, %cr18 /* IIAOQ head */
217 mtctl %r1, %cr18 /* IIAOQ tail */
[all …]
Dhpmc.S141 mtctl %r4,ipsw
142 mtctl %r0,pcsq
143 mtctl %r0,pcsq
145 mtctl %r4,pcoq
147 mtctl %r4,pcoq
250 mtctl %r4,%cr24 /* Initialize kernel root pointer */
251 mtctl %r4,%cr25 /* Initialize user root pointer */
Dpacache.S67 mtctl %r0, %cr17 /* Clear IIASQ tail */
68 mtctl %r0, %cr17 /* Clear IIASQ head */
69 mtctl %r1, %cr18 /* IIAOQ head */
71 mtctl %r1, %cr18 /* IIAOQ tail */
73 mtctl %r1, %ipsw
178 mtctl %r0, %cr17 /* Clear IIASQ tail */
179 mtctl %r0, %cr17 /* Clear IIASQ head */
180 mtctl %r1, %cr18 /* IIAOQ head */
182 mtctl %r1, %cr18 /* IIAOQ tail */
185 mtctl %r1, %ipsw /* restore I-bit (entire PSW) */
[all …]
Dtime.c118 mtctl(next_tick, 16); in timer_interrupt()
161 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ in start_cpu_itimer()
Dperf_asm.S56 mtctl %r26,ccr ; turn on performance coprocessor
61 mtctl %r26,ccr ; turn off performance coprocessor
82 mtctl %r26,ccr ; turn on performance coprocessor
87 mtctl %r26,ccr ; turn off performance coprocessor
Dentry.S82 mtctl %r0, %cr17 /* Clear IIASQ tail */
83 mtctl %r0, %cr17 /* Clear IIASQ head */
84 mtctl %r1, %ipsw
86 mtctl %r1, %cr18 /* Set IIAOQ tail */
88 mtctl %r1, %cr18 /* Set IIAOQ head */
819 mtctl %r25,%cr30
822 mtctl %r0, %cr0 /* Needed for single stepping */
1382 mtctl %r8,%ipsw
1758 mtctl %r3, %cr27
1912 mtctl %r2,%cr0 /* for immediate trap */
Dirq.c95 mtctl(mask, 23); in cpu_ack_irq()
600 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ in init_IRQ()
Dsetup.c418 mtctl(coproc_cfg.ccr_functional, 10); in start_parisc()
Dprocessor.c329 mtctl(coproc_cfg.ccr_functional, 10); /* 10 == Coprocessor Control Reg */ in init_per_cpu()
Dsignal.c382 mtctl(-1, 0); in setup_rt_frame()
Dsyscall.S94 mtctl %r26, %cr27 /* move arg0 to the control register */
/arch/parisc/include/asm/
Dspecial_insns.h14 #define mtctl(gr, cr) \ macro
24 mtctl(val, 15); in set_eiem()
Dmmu_context.h50 mtctl(__space_to_prot(context), 8); in load_context()
57 mtctl(__pa(next->pgd), 25); in switch_mm_irqs_off()
Dassembly.h178 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
383 mtctl %r3, %cr27
427 mtctl %r3, %cr27
443 mtctl %r0, %cr17
447 mtctl %r0, %cr18