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Searched refs:mtdcr (Results 1 – 7 of 7) sorted by relevance

/arch/powerpc/platforms/4xx/
Dsoc.c38 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr); in l2c_diag()
39 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG); in l2c_diag()
65 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in l2c_error_handler()
66 mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE); in l2c_error_handler()
129 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC, in ppc4xx_l2c_probe()
131 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR, in ppc4xx_l2c_probe()
133 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR, in ppc4xx_l2c_probe()
135 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR, in ppc4xx_l2c_probe()
137 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR, in ppc4xx_l2c_probe()
144 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); in ppc4xx_l2c_probe()
[all …]
Duic.c65 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
68 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
82 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_irq()
93 mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); in uic_ack_irq()
108 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_ack_irq()
118 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
159 mtdcr(uic->dcrbase + UIC_PR, pr); in uic_set_irq_type()
160 mtdcr(uic->dcrbase + UIC_TR, tr); in uic_set_irq_type()
161 mtdcr(uic->dcrbase + UIC_SR, ~mask); in uic_set_irq_type()
267 mtdcr(uic->dcrbase + UIC_ER, 0); in uic_init_one()
[all …]
/arch/powerpc/boot/
Ddcr.h11 #define mtdcr(rn, val) \ macro
29 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
32 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
33 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
182 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
185 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
186 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
200 mtdcr(DCRN_CPR0_CFGADDR, offset); \
203 mtdcr(DCRN_CPR0_CFGADDR, offset); \
204 mtdcr(DCRN_CPR0_CFGDATA, data); })
D4xx.c300 mtdcr(DCRN_MAL0_CFG, MAL_RESET); in ibm4xx_quiesce_eth()
316 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); in ibm4xx_fixup_ebc_ranges()
613 mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); in ibm405gp_fixup_clocks()
/arch/powerpc/sysdev/
Ddcr-low.S41 mtdcr 0,r4; blr
46 mtdcr dcr,r4; blr
/arch/powerpc/include/asm/
Ddcr-native.h42 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
76 #define mtdcr(rn, v) \ macro
/arch/powerpc/kernel/
Dcpu_setup_44x.S71 mtdcr DCRN_PLB4A0_ACR,r3