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Searched refs:outb (Results 1 – 25 of 130) sorted by relevance

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/arch/arm/mach-footbridge/
Dcats-hw.c32 outb(0x51, CFG_PORT); in cats_hw_init()
33 outb(0x23, CFG_PORT); in cats_hw_init()
36 outb(0x07, INDEX_PORT); in cats_hw_init()
37 outb(0x03, DATA_PORT); in cats_hw_init()
41 outb(0x74, INDEX_PORT); in cats_hw_init()
42 outb(0x03, DATA_PORT); in cats_hw_init()
44 outb(0xf0, INDEX_PORT); in cats_hw_init()
45 outb(0x0f, DATA_PORT); in cats_hw_init()
47 outb(0xf1, INDEX_PORT); in cats_hw_init()
48 outb(0x07, DATA_PORT); in cats_hw_init()
[all …]
Disa-irq.c37 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); in isa_mask_pic_lo_irq()
44 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); in isa_ack_pic_lo_irq()
45 outb(0x20, PIC_LO); in isa_ack_pic_lo_irq()
52 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); in isa_unmask_pic_lo_irq()
65 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); in isa_mask_pic_hi_irq()
72 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); in isa_ack_pic_hi_irq()
73 outb(0x62, PIC_LO); in isa_ack_pic_hi_irq()
74 outb(0x20, PIC_HI); in isa_ack_pic_hi_irq()
81 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); in isa_unmask_pic_hi_irq()
128 outb(0x11, PIC_LO); in isa_init_irq()
[all …]
Dnetwinder-hw.c37 outb(0x87, 0x370); in wb977_open()
38 outb(0x87, 0x370); in wb977_open()
43 outb(0xaa, 0x370); in wb977_close()
48 outb(reg, 0x370); in wb977_wb()
49 outb(val, 0x371); in wb977_wb()
54 outb(reg, 0x370); in wb977_ww()
55 outb(val >> 8, 0x371); in wb977_ww()
56 outb(reg + 1, 0x370); in wb977_ww()
57 outb(val & 255, 0x371); in wb977_ww()
83 outb(new_gpio, GP1_IO_BASE); in nw_gpio_modify_op()
[all …]
/arch/arm/kernel/
Ddma-isa.c100 outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); in isa_enable_dma()
101 outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); in isa_enable_dma()
108 outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); in isa_enable_dma()
110 outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); in isa_enable_dma()
111 outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]); in isa_enable_dma()
113 outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); in isa_enable_dma()
114 outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); in isa_enable_dma()
116 outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); in isa_enable_dma()
119 outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]); in isa_enable_dma()
124 outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]); in isa_disable_dma()
[all …]
/arch/alpha/kernel/
Dsmc37c93x.c97 outb(CONFIG_ON_KEY, configPort); in SMCConfigState()
98 outb(CONFIG_ON_KEY, configPort); in SMCConfigState()
99 outb(DEVICE_ID, indexPort); in SMCConfigState()
102 outb(DEVICE_REV, indexPort); in SMCConfigState()
114 outb(CONFIG_OFF_KEY, baseAddr); in SMCRunState()
143 outb(LOGICAL_DEVICE_NUMBER, indexPort); in SMCEnableDevice()
144 outb(device, dataPort); in SMCEnableDevice()
146 outb(ADDR_LO, indexPort); in SMCEnableDevice()
147 outb(( portaddr & 0xFF ), dataPort); in SMCEnableDevice()
149 outb(ADDR_HI, indexPort); in SMCEnableDevice()
[all …]
Dsys_ruffian.c43 outb(0x11,0xA0); in ruffian_init_irq()
44 outb(0x08,0xA1); in ruffian_init_irq()
45 outb(0x02,0xA1); in ruffian_init_irq()
46 outb(0x01,0xA1); in ruffian_init_irq()
47 outb(0xFF,0xA1); in ruffian_init_irq()
49 outb(0x11,0x20); in ruffian_init_irq()
50 outb(0x00,0x21); in ruffian_init_irq()
51 outb(0x04,0x21); in ruffian_init_irq()
52 outb(0x01,0x21); in ruffian_init_irq()
53 outb(0xFF,0x21); in ruffian_init_irq()
[all …]
Des1888.c29 outb(0x01, 0x0226); /* reset */ in es1888_init()
31 outb(0x00, 0x0226); /* release reset */ in es1888_init()
35 outb(0xc6, 0x022c); /* enable extended mode */ in es1888_init()
39 outb(0xb1, 0x022c); /* setup for write to Interrupt CR */ in es1888_init()
42 outb(0x14, 0x022c); /* set IRQ 5 */ in es1888_init()
45 outb(0xb2, 0x022c); /* setup for write to DMA CR */ in es1888_init()
48 outb(0x18, 0x022c); /* set DMA channel 1 */ in es1888_init()
Dsys_sio.c154 outb((level_bits >> 0) & 0xff, 0x4d0); in __sio_fixup_irq_levels()
155 outb((level_bits >> 8) & 0xff, 0x4d1); in __sio_fixup_irq_levels()
292 outb(ctest4 | 0x80, io_port+0x21); in alphabook1_init_pci()
301 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */ in alphabook1_init_pci()
302 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */ in alphabook1_init_pci()
303 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */ in alphabook1_init_pci()
307 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */ in alphabook1_init_pci()
309 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */ in alphabook1_init_pci()
Dtime.c237 outb(0x36, 0x43); /* pit counter 0: system timer */ in common_init_rtc()
238 outb(0x00, 0x40); in common_init_rtc()
239 outb(0x00, 0x40); in common_init_rtc()
241 outb(0xb6, 0x43); /* pit counter 2: speaker */ in common_init_rtc()
242 outb(0x31, 0x42); in common_init_rtc()
243 outb(0x13, 0x42); in common_init_rtc()
349 outb((inb(0x61) & ~0x02) | 0x01, 0x61); in calibrate_cc_with_pit()
358 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ in calibrate_cc_with_pit()
359 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ in calibrate_cc_with_pit()
360 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ in calibrate_cc_with_pit()
Dpc873xx.c28 outb(reg, base); in pc873xx_read()
37 outb(reg, base); in pc873xx_write()
38 outb(data, base + 1); in pc873xx_write()
39 outb(data, base + 1); /* Must be written twice */ in pc873xx_write()
Dsys_sx164.c40 outb(0, DMA1_RESET_REG); in sx164_init_irq()
41 outb(0, DMA2_RESET_REG); in sx164_init_irq()
42 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); in sx164_init_irq()
43 outb(0, DMA2_MASK_REG); in sx164_init_irq()
Dirq_i8259.c33 outb(mask, port); in i8259_update_irq_hw()
68 outb(0xE0 | (irq - 8), 0xa0); /* ack the slave */ in i8259a_mask_and_ack_irq()
71 outb(0xE0 | irq, 0x20); /* ack the master */ in i8259a_mask_and_ack_irq()
92 outb(0xff, 0x21); /* mask all of 8259A-1 */ in init_i8259a_irqs()
93 outb(0xff, 0xA1); /* mask all of 8259A-2 */ in init_i8259a_irqs()
/arch/powerpc/sysdev/
Di8259.c48 outb(0x0C, 0x20); /* prepare for poll */ in i8259_irq()
55 outb(0x0C, 0xA0); /* prepare for poll */ in i8259_irq()
69 outb(0x0B, 0x20); /* ISR register */ in i8259_irq()
88 outb(cached_A1, 0xA1); in i8259_mask_and_ack_irq()
89 outb(0x20, 0xA0); /* Non-specific EOI */ in i8259_mask_and_ack_irq()
90 outb(0x20, 0x20); /* Non-specific EOI to cascade */ in i8259_mask_and_ack_irq()
94 outb(cached_21, 0x21); in i8259_mask_and_ack_irq()
95 outb(0x20, 0x20); /* Non-specific EOI */ in i8259_mask_and_ack_irq()
102 outb(cached_A1,0xA1); in i8259_set_irq_mask()
103 outb(cached_21,0x21); in i8259_set_irq_mask()
[all …]
/arch/x86/kernel/
Di8259.c66 outb(cached_slave_mask, PIC_SLAVE_IMR); in mask_8259A_irq()
68 outb(cached_master_mask, PIC_MASTER_IMR); in mask_8259A_irq()
85 outb(cached_slave_mask, PIC_SLAVE_IMR); in unmask_8259A_irq()
87 outb(cached_master_mask, PIC_MASTER_IMR); in unmask_8259A_irq()
132 outb(0x0B, PIC_MASTER_CMD); /* ISR register */ in i8259A_irq_real()
134 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ in i8259A_irq_real()
137 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ in i8259A_irq_real()
139 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ in i8259A_irq_real()
178 outb(cached_slave_mask, PIC_SLAVE_IMR); in mask_and_ack_8259A()
180 outb(0x60+(irq&7), PIC_SLAVE_CMD); in mask_and_ack_8259A()
[all …]
/arch/x86/include/asm/
Dprocessor-cyrix.h23 outb(reg, 0x22); in getCx86()
29 outb(reg, 0x22); in setCx86()
30 outb(data, 0x23); in setCx86()
33 #define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
36 outb((reg), 0x22); \
37 outb((data), 0x23); \
Dmach_traps.h34 outb(0x8f, 0x70); in reassert_nmi()
36 outb(0x0f, 0x70); in reassert_nmi()
39 outb(old_reg, 0x70); in reassert_nmi()
/arch/x86/boot/
Dearly_serial_console.c31 outb(0x3, port + LCR); /* 8n1 */ in early_serial_init()
32 outb(0, port + IER); /* no interrupt */ in early_serial_init()
33 outb(0, port + FCR); /* no fifo */ in early_serial_init()
34 outb(0x3, port + MCR); /* DTR + RTS */ in early_serial_init()
38 outb(c | DLAB, port + LCR); in early_serial_init()
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
40 outb((divisor >> 8) & 0xff, port + DLH); in early_serial_init()
41 outb(c & ~DLAB, port + LCR); in early_serial_init()
108 outb(lcr | DLAB, port + LCR); in probe_baud()
111 outb(lcr, port + LCR); in probe_baud()
Dpm.c30 outb(0x80, 0x70); /* Disable NMI */ in realmode_switch_hook()
40 outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */ in mask_all_interrupts()
42 outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ in mask_all_interrupts()
51 outb(0, 0xf0); in reset_coprocessor()
53 outb(0, 0xf1); in reset_coprocessor()
Da20.c104 outb(0xd1, 0x64); /* Command write */ in enable_a20_kbc()
107 outb(0xdf, 0x60); /* A20 on */ in enable_a20_kbc()
110 outb(0xff, 0x64); /* Null command, but UHCI wants it */ in enable_a20_kbc()
121 outb(port_a, 0x92); in enable_a20_fast()
/arch/x86/pci/
Ddirect.c66 outb((u8)value, 0xCFC + (reg & 3)); in pci_conf1_write()
115 outb((u8)(0xF0 | (fn << 1)), 0xCF8); in pci_conf2_read()
116 outb((u8)bus, 0xCFA); in pci_conf2_read()
130 outb(0, 0xCF8); in pci_conf2_read()
155 outb((u8)(0xF0 | (fn << 1)), 0xCF8); in pci_conf2_write()
156 outb((u8)bus, 0xCFA); in pci_conf2_write()
160 outb((u8)value, PCI_CONF2_ADDRESS(dev, reg)); in pci_conf2_write()
170 outb(0, 0xCF8); in pci_conf2_write()
232 outb(0x01, 0xCFB); in pci_check_type1()
251 outb(0x00, 0xCFB); in pci_check_type2()
[all …]
/arch/mips/loongson64/lemote-2f/
Dec_kb3310b.c29 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); in ec_read()
30 outb((addr & 0x00ff), EC_IO_PORT_LOW); in ec_read()
43 outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); in ec_write()
44 outb((addr & 0x00ff), EC_IO_PORT_LOW); in ec_write()
45 outb(val, EC_IO_PORT_DATA); in ec_write()
66 outb(cmd, EC_CMD_PORT); in ec_query_seq()
/arch/x86/realmode/rm/
Dwakemain.c20 outb(0xb6, 0x43); /* Ctr 2, squarewave, load, binary */ in beep()
22 outb(div, 0x42); /* LSB of counter */ in beep()
24 outb(div >> 8, 0x42); /* MSB of counter */ in beep()
31 outb(enable, 0x61); /* Enable timer 2 output to speaker */ in beep()
/arch/mips/sgi-ip22/
Dip22-eisa.c89 outb(0x20, EISA_INT2_CTRL); in ip22_eisa_intr()
90 outb(0x20, EISA_INT1_CTRL); in ip22_eisa_intr()
132 outb(1, EISA_EXT_NMI_RESET_CTRL); in ip22_eisa_init()
134 outb(0, EISA_EXT_NMI_RESET_CTRL); in ip22_eisa_init()
135 outb(0, EISA_DMA2_WRITE_SINGLE); in ip22_eisa_init()
/arch/mips/include/asm/mach-malta/
Dmc146818rtc.h34 outb(addr, MALTA_RTC_ADR_REG); in CMOS_READ()
40 outb(addr, MALTA_RTC_ADR_REG); in CMOS_WRITE()
41 outb(data, MALTA_RTC_DAT_REG); in CMOS_WRITE()
/arch/mips/loongson64/common/
Dpm.c35 outb(0xff, PIC_SLAVE_IMR); in arch_suspend_disable_irqs()
37 outb(0xff, PIC_MASTER_IMR); in arch_suspend_disable_irqs()
52 outb(cached_slave_mask, PIC_SLAVE_IMR); in arch_suspend_enable_irqs()
53 outb(cached_master_mask, PIC_MASTER_IMR); in arch_suspend_enable_irqs()

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