| /arch/microblaze/lib/ |
| D | fastcopy.S | 83 lwi r12, r6, 12 /* t4 = *(s + 12) */
87 swi r12, r5, 12 /* *(d + 12) = t4 */
91 lwi r12, r6, 28 /* t4 = *(s + 28) */
95 swi r12, r5, 28 /* *(d + 28) = t4 */
115 lwi r12, r8, 4 /* v = *(as + 4) */
116 bsrli r9, r12, 8 /* t1 = v >> 8 */
119 bslli r11, r12, 24 /* h = v << 24 */
120 lwi r12, r8, 8 /* v = *(as + 8) */
121 bsrli r9, r12, 8 /* t1 = v >> 8 */
124 bslli r11, r12, 24 /* h = v << 24 */
[all …]
|
| /arch/powerpc/include/asm/ |
| D | exception-64e.h | 99 mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
100 mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
101 std r10,EX_TLB_R10(r12); \
103 std r11,EX_TLB_R11(r12); \
105 std r13,EX_TLB_R13(r12); \
107 std r14,EX_TLB_R14(r12); \
108 addi r14,r12,EX_TLB_SIZE; \
109 std r15,EX_TLB_R15(r12); \
111 std r16,EX_TLB_R16(r12); \
113 std r10,EX_TLB_CR(r12); \
[all …]
|
| /arch/arc/lib/ |
| D | strchr-700.S | 34 sub r12,r2,r7
35 bic_s r12,r12,r2
36 and r12,r12,r4
37 brne.d r12,0,.Lfound0_ua
40 sub r12,r6,r7
41 bic r12,r12,r6
43 and r7,r12,r4
47 and r12,r12,r4
48 breq r12,0,.Loop ; For speed, we want this branch to be unaligned.
49 lsr_s r12,r12,7
[all …]
|
| D | strlen.S | 25 sub r12,r6,r7
26 bic r12,r12,r6
27 or.eq r12,r12,r1
28 and r12,r12,r5
29 brne r12,0,.Learly_end
38 sub r12,r6,r4
39 bic r12,r12,r6
40 bmsk.ne r12,r12,r7
41 or.eq r12,r12,r1
42 and r12,r12,r5
[all …]
|
| D | memcpy-700.S | 17 ld_s r12,[r1,0]
21 st.ab r12,[r5,4]
22 ld.a r12,[r1,4]
26 st.ab r12,[r5,4]
27 ld.a r12,[r1,8]
35 xor_s r12,r12,r3
36 bmsk r12,r12,r2
37 xor_s r12,r12,r3
41 xor_s r3,r3,r12
43 xor_s r12,r12,r3
[all …]
|
| D | memcmp.S | 20 or r12,r0,r1
21 asl_s r12,r12,30
23 brls r2,r12,.Lbytewise
34 mov_s r12,WORD2
36 brne WORD2,r12,.Lodd
42 ld_s r12,[r1,4]
48 brne WORD2,r12,.Lodd
50 brne WORD2,r12,.Lodd
78 asl r12,r5,r1
80 lsr_s r12,r12,1
[all …]
|
| /arch/powerpc/platforms/pseries/ |
| D | hvCall.S | 94 ld r12,hcall_tracepoint_refcount@toc(r2); \
95 std r12,32(r1); \
96 cmpdi r12,0; \
149 ld r12,STK_PARAM(R4)(r1)
150 std r4, 0(r12)
151 std r5, 8(r12)
152 std r6, 16(r12)
153 std r7, 24(r12)
176 ld r12,STK_PARAM(R4)(r1)
177 std r4,0(r12)
[all …]
|
| /arch/powerpc/kvm/ |
| D | book3s_rmhandlers.S | 68 mtspr SPRN_SPRG_SCRATCH1, r12 /* Save r12 */
69 mfcr r12
72 2: mtcr r12
73 mfspr r12, SPRN_SPRG_SCRATCH1
78 stw r12, HSTATE_SCRATCH1(r13)
79 mfspr r12, SPRN_SPRG_SCRATCH1
80 stw r12, HSTATE_SCRATCH0(r13)
81 lbz r12, HSTATE_IN_GUEST(r13)
82 cmpwi r12, KVM_GUEST_MODE_NONE
85 lwz r12, HSTATE_SCRATCH1(r13)
[all …]
|
| /arch/arm/mach-omap2/ |
| D | omap-smc.S | 28 stmfd sp!, {r2-r12, lr}
29 mov r12, r0
33 ldmfd sp!, {r2-r12, pc}
45 stmfd sp!, {r4-r12, lr}
50 mov r12, #0x00 @ Secure Service ID
56 ldmfd sp!, {r4-r12, pc}
69 mov r12, r0 @ Copy the secure service ID
77 stmfd sp!, {r1-r12, lr}
78 ldr r12, =0x104
81 ldmfd sp!, {r1-r12, pc}
[all …]
|
| /arch/cris/arch-v32/lib/ |
| D | checksum.S | 15 ;; r12 - checksum
33 addc $r0,$r12
34 addc $r1,$r12
35 addc $r2,$r12
36 addc $r3,$r12
37 addc $r4,$r12
38 addc $r5,$r12
39 addc $r6,$r12
40 addc $r7,$r12
41 addc $r8,$r12
[all …]
|
| /arch/arm/mach-imx/ |
| D | ssi-fiq.S | 45 ldr r12, .L_imx_ssi_fiq_base
51 ldr r11, [r12, #SSI_SIER]
56 ldr r11, [r12, #SSI_SISR]
67 strh r11, [r12, #SSI_STX0]
70 strh r11, [r12, #SSI_STX0]
73 strh r11, [r12, #SSI_STX0]
76 strh r11, [r12, #SSI_STX0]
87 ldr r11, [r12, #SSI_SIER]
92 ldr r11, [r12, #SSI_SISR]
104 ldr r11, [r12, #SSI_SACNT]
[all …]
|
| /arch/powerpc/kernel/ |
| D | head_40x.S | 122 stw r12,GPR12(r11); \
126 mfspr r12,SPRN_SPRG_SCRATCH1; \
127 stw r12,GPR11(r11); \
131 mfspr r12,SPRN_SRR0; \
164 stw r12,GPR12(r11); \
168 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
169 stw r12,_DEAR(r11); /* since they may have had stuff */\
172 mfspr r12,SPRN_SRR2; \
267 stw r12, 0(r0)
270 mfspr r12, SPRN_PID
[all …]
|
| D | head_44x.S | 311 mtspr SPRN_SPRG_WSCRATCH2, r12
326 mfspr r12,SPRN_MMUCR
327 rlwinm r12,r12,0,0,23 /* Clear TID */
337 mfspr r12,SPRN_MMUCR
339 rlwimi r12,r13,0,24,31 /* Set TID */
342 mtspr SPRN_MMUCR,r12
357 mfspr r12,SPRN_ESR
359 rlwimi r13,r12,10,30,30
363 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
364 lwzx r11, r12, r11 /* Get pgd/pmd entry */
[all …]
|
| D | reloc_32.S | 38 0: mflr r12 /* Make it accessible */
41 lwz r11, (p_dyn - 0b)(r12)
42 add r11, r11, r12 /* runtime address of .dynamic section */
43 lwz r9, (p_rela - 0b)(r12)
44 add r9, r9, r12 /* runtime address of .rela.dyn section */
45 lwz r10, (p_st - 0b)(r12)
46 add r10, r10, r12 /* runtime address of _stext section */
47 lwz r13, (p_sym - 0b)(r12)
48 add r13, r13, r12 /* runtime address of .dynsym section */
94 subf r12, r7, r10
[all …]
|
| D | head_fsl_booke.S | 316 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
317 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
318 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
323 xor r12, r10, r11; /* drop size bits from pointer */ \
325 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
327 1001: lwz r11, 4(r12); /* Get pte entry */
330 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
331 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
332 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
334 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
[all …]
|
| /arch/x86/mm/ |
| D | mem_encrypt_boot.S | 44 push %r12
47 movq %rdx, %r12 /* Area length */
59 movq %r12, %rcx /* Area length */
66 pop %r12
109 push %r12
126 movq $PMD_PAGE_SIZE, %r12
128 cmpq %r12, %r9
130 movq %r9, %r12
135 movq %r12, %rcx
140 movq %r12, %rcx
[all …]
|
| /arch/cris/arch-v10/lib/ |
| D | checksum.S | 14 ;; r12 - checksum
40 add.d $r0,$r12
42 add.d $r1,$r12
44 add.d $r2,$r12
46 add.d $r3,$r12
48 add.d $r4,$r12
50 add.d $r5,$r12
52 add.d $r6,$r12
54 add.d $r7,$r12
56 add.d $r8,$r12
[all …]
|
| /arch/powerpc/lib/ |
| D | crtsavres.S | 443 li r12,-192
444 stvx v20,r12,r0
447 li r12,-176
448 stvx v21,r12,r0
451 li r12,-160
452 stvx v22,r12,r0
455 li r12,-144
456 stvx v23,r12,r0
459 li r12,-128
460 stvx v24,r12,r0
[all …]
|
| D | checksum_32.S | 94 adde r12,r12,r7; \
97 adde r12,r12,r8; \
100 adde r12,r12,r9; \
103 adde r12,r12,r10
129 addic r12,r6,0
140 rlwnm r12,r12,r7,0,31 /* odd destination address: rotate one byte */
153 adde r12,r12,r3
159 adde r12,r12,r9
221 adde r12,r12,r0
230 adde r12,r12,r0
[all …]
|
| /arch/powerpc/boot/ |
| D | opal-calls.S | 37 mfcr r12
38 stw r12,8(r1)
44 mfmsr r12
48 andc r12,r12,r11
49 mtspr SPRN_HSRR1,r12
53 ld r12,8(r11)
55 mtspr SPRN_HSRR0,r12
62 ld r12,16(r1)
64 mtlr r12
|
| /arch/arm/lib/ |
| D | floppydma.S | 17 ldrgtb r12, [r11, #-4]
18 ldrleb r12, [r11], #0
19 strb r12, [r10], #1
26 ldrgeb r12, [r10], #1
27 movlt r12, #0
28 strleb r12, [r11], #0
30 strb r12, [r11, #-4]
|
| /arch/powerpc/kernel/trace/ |
| D | ftrace_64_mprofile.S | 187 CURRENT_THREAD_INFO(r12, r1)
190 ld r11, TI_livepatch_sp(r12)
192 std r11, TI_livepatch_sp(r12)
196 mflr r12
197 std r12, -16(r11)
200 lis r12, STACK_END_MAGIC@h
201 ori r12, r12, STACK_END_MAGIC@l
202 std r12, -8(r11)
205 mfctr r12
214 CURRENT_THREAD_INFO(r12, r1)
[all …]
|
| /arch/arm/crypto/ |
| D | sha256-core.S_shipped | 96 ldr r12,.LOPENSSL_armcap
97 ldr r12,[r3,r12] @ OPENSSL_armcap_P
98 tst r12,#ARMV8_SHA256
100 tst r12,#ARMV7_NEON
115 eor r12,r12,r12
122 add r4,r4,r12 @ h+=Maj(a,b,c) from the past
129 add r4,r4,r12 @ h+=Maj(a,b,c) from the past
130 ldrb r12,[r1,#2]
132 orr r2,r2,r12,lsl#8
133 ldrb r12,[r1],#4
[all …]
|
| /arch/arm/mach-rpc/ |
| D | fiq.S | 11 mov r12, #ioc_base_high
13 orr r12, r12, #ioc_base_low
15 strb r12, [r12, #0x38] @ Disable FIQ register
|
| /arch/arm/mach-s3c24xx/ |
| D | sleep.S | 69 ldr r12, [ r14, #0x54 ]
70 bic r12, r12, #3<<4
71 orr r12, r12, #1<<7
72 str r12, [ r14, #0x54 ]
|