| /arch/sh/lib64/ |
| D | udivsi3.S | 18 mmulfx.w r21,r21,r19
21 mmulfx.w r25,r19,r19
24 msub.w r21,r19,r19
31 addi r19,-2,r21
33 mmulfx.w r19,r19,r19
37 mmacnfx.wl r25,r19,r21
41 mulu.l r25,r21,r19
44 shlrd r19,r0,r19
45 mulu.l r19,r22,r20
46 add r18,r19,r18
[all …]
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| D | sdivsi3.S | 21 ldx.ub r20, r21, r19 /* u0.8 */
24 muls.l r25, r19, r19 /* s2.38 */
27 shari r19, 24, r19 /* truncate to s2.14 */
28 sub r21, r19, r19 /* some 11 bit inverse in s1.14 */
29 muls.l r19, r19, r21 /* u0.28 */
33 shlli r19, 45, r19 /* multiply by two and convert to s2.58 */
35 sub r19, r18, r18
40 shari r0, 16, r19 /* s-16.44 */
41 muls.l r19, r18, r19 /* s-16.74 */
44 shari r19, 30, r19 /* s-16.44 */
[all …]
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| /arch/openrisc/lib/ |
| D | memset.S | 45 1: l.addi r19, r3, 0 // Set r19 = src
56 l.addi r19, r3, 0 // Set r19 = src
64 l.addi r19, r3, 1 // src += 1
72 l.addi r19, r3, 2 // src += 2
77 l.addi r19, r3, 3 // src += 3
80 2: l.sw 0(r19), r13 // *src = cccc
84 l.addi r19, r19, 4 // Increase src
92 l.sb 0(r19), r13 // *src = cccc
95 l.addi r19, r19, 1 // Increase src
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| /arch/unicore32/lib/ |
| D | copy_page.S | 27 stm.w (r17 - r19, lr), [sp-]
30 mov r19, #COPY_COUNT
36 sub.a r19, r19, #1
38 ldm.w (r17 - r19, pc), [sp]+
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| /arch/ia64/kernel/ |
| D | ivt.S | 83 mov r19=n;; /* prepare to save predicates */ \
122 mov r19=IA64_KR(PT_BASE) // get page table base address
140 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
143 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
149 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
174 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
177 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr)
180 MOV_FROM_ISR(r19) // cr.isr bit 32 tells us if this is an insn miss
185 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
229 ld8 r19=[r28] // read *pud again
[all …]
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| D | mca_asm.S | 69 ld4 r19=[r2],4 // r19=ptce_count[0]
81 cmp.ltu p6,p7=r24,r19
124 movl r19=PAGE_OFFSET
126 add r16=r19,r16
144 mov r19=1 // All MCA events are treated as monarch (for now)
175 mov r19=ip
178 dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT
197 mov r19=IA64_GRANULE_SHIFT<<2
199 mov cr.itir=r19
211 movl r19=PAGE_OFFSET
[all …]
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| D | esi_stub.S | 84 .ret0: mov loc5=r19 // old ar.bsp
89 mov r19=loc5 // save virtual mode bspstore
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| D | efi_stub.S | 74 mov loc5=r19
79 mov r19=loc5
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| D | gate.S | 200 .save ar.rnat, r19
201 mov r19=ar.rnat // save RNaT before switching backing store area
209 st8 [r14]=r19 // save sc_ar_rnat
223 (p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now
334 mov r19=NR_syscalls-1 // A
339 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)?
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| D | relocate_kernel.S | 70 ld4 r19=[r2],4 // r19=ptce_count[0]
81 cmp.ltu p6,p7=r24,r19
120 movl r19=PAGE_OFFSET
122 add r16=r19,r16
274 st8 [in0]=r19, 8 // r19
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| D | pal.S | 182 mov loc5 = r19
188 mov r19=loc5
239 mov loc5 = r19
246 mov r19=loc5
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| D | head.S | 337 mov r19=IA64_TR_CURRENT_STACK
339 itr.d dtr[r19]=r18
363 movl r19=__phys_per_cpu_start
367 add r19=r19,r18
375 ld8 r21=[r19],8;;
380 mov r19=r20
384 tpa r19=r19
387 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
431 add r19=IA64_NUM_DBG_REGS*8,in0
442 st8.nta [r19]=r17,8
[all …]
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| /arch/parisc/kernel/ |
| D | syscall.S | 168 STREG %r19, TASK_PT_GR19(%r1)
172 extrd,u %r2,63,1,%r19 /* W hidden in bottom bit */
174 xor %r19,%r2,%r2 /* clear bottom bit */
175 depd,z %r19,1,1,%r19
176 std %r19,TASK_PT_PSW(%r1)
204 copy %r19,%r2 /* W bit back to r2 */
215 ldi _TIF_SYSCALL_TRACE_MASK, %r19
216 and,COND(=) %r1, %r19, %r0
226 ldo R%sys_call_table(%r1), %r19
228 ldo R%sys_call_table64(%r1), %r19
[all …]
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| D | pacache.S | 58 rsm PSW_SM_I, %r19 /* save I-bit state */
184 or %r1, %r19, %r1 /* I-bit to state on entry */
449 1: ldd 0(%r25), %r19
454 std %r19, 0(%r26)
457 ldd 32(%r25), %r19
464 std %r19, 32(%r26)
467 ldd 64(%r25), %r19
474 std %r19, 64(%r26)
477 ldd 96(%r25), %r19
485 std %r19, 96(%r26)
[all …]
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| D | entry.S | 854 LDREG PT_IAOQ0(%r16),%r19
855 depi 3,31,2,%r19
856 STREG %r19,PT_IAOQ0(%r16)
857 LDREG PT_IAOQ1(%r16),%r19
858 depi 3,31,2,%r19
859 STREG %r19,PT_IAOQ1(%r16)
860 LDREG PT_PSW(%r16),%r19
866 and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
868 or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
869 STREG %r19,PT_PSW(%r16)
[all …]
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| /arch/microblaze/kernel/ |
| D | entry-nommu.S | 87 swi r19, r1, PT_R19
129 lwi r19, r6, TI_FLAGS /* get flags in thread info */
132 andi r11, r19, _TIF_NEED_RESCHED
137 1: andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME
177 lwi r19, r1, PT_R19
241 swi r19, r1, PT_R19
332 swi r19, r1, PT_R19
406 swi r19, r11, CC_R19
456 lwi r19, r11, CC_R19
485 addk r5, r0, r19
[all …]
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| D | entry.S | 195 swi r19, r1, PT_R19; \
229 lwi r19, r1, PT_R19; \
416 lwi r19, r11, TI_FLAGS; /* get flags in thread info */
417 andi r11, r19, _TIF_NEED_RESCHED;
426 andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME;
475 addk r5, r0, r19 /* ... and argument - in r19 */
590 lwi r19, r11, TI_FLAGS; /* get flags in thread info */
591 andi r11, r19, _TIF_NEED_RESCHED;
600 5: andi r11, r19, _TIF_SIGPENDING | _TIF_NOTIFY_RESUME;
702 lwi r19, r11, TI_FLAGS; /* MS: get flags from thread info */
[all …]
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| /arch/alpha/kernel/ |
| D | signal.c | 178 err |= __get_user(regs->r19, sc->sc_regs+19); in restore_sigcontext()
313 err |= __put_user(regs->r19, sc->sc_regs+19); in setup_sigcontext()
458 syscall_restart(unsigned long r0, unsigned long r19, in syscall_restart() argument
471 regs->r19 = r19; in syscall_restart()
495 do_signal(struct pt_regs *regs, unsigned long r0, unsigned long r19) in do_signal() argument
506 syscall_restart(r0, r19, regs, &ksig.ka); in do_signal()
517 regs->r19 = r19; in do_signal()
535 unsigned long r0, unsigned long r19) in do_work_pending() argument
543 do_signal(regs, r0, r19); in do_work_pending()
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| /arch/powerpc/lib/ |
| D | copypage_power7.S | 121 std r19,STK_REG(R19)(r1)
138 ld r19,112(r4)
155 std r19,112(r3)
165 ld r19,STK_REG(R19)(r1)
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| /arch/microblaze/lib/ |
| D | uaccess_old.S | 108 2: lwi r19, r6, 0x0004 + offset; \
116 10: swi r19, r5, 0x0004 + offset; \
196 swi r19, r1, 12
219 lwi r19, r1, 12
239 lwi r19, r1, 12
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| /arch/ia64/lib/ |
| D | xor.S | 120 mov r19 = in4
129 (p[0]) ld8.nta s4[0] = [r19], 8
164 mov r19 = in4
174 (p[0]) ld8.nta s4[0] = [r19], 8
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| /arch/alpha/include/uapi/asm/ |
| D | ptrace.h | 30 unsigned long r19; member
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| /arch/arc/include/asm/ |
| D | unwind.h | 36 unsigned long r19; member
95 PTREGS_INFO(r19), \
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| /arch/arc/include/uapi/asm/ |
| D | ptrace.h | 46 unsigned long r19, r18, r17, r16, r15, r14, r13; member
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| /arch/hexagon/include/uapi/asm/ |
| D | user.h | 33 unsigned long r19; member
|