| /arch/unicore32/kernel/ |
| D | clock.c | 32 unsigned long rate; member
38 .rate = CLOCK_TICK_RATE,
95 return clk->rate; in clk_get_rate()
100 unsigned long rate; member
104 {.rate = 25175000, .cfg = 0x00002001, .div = 0x9},
105 {.rate = 31500000, .cfg = 0x00002001, .div = 0x7},
106 {.rate = 40000000, .cfg = 0x00003801, .div = 0x9},
107 {.rate = 49500000, .cfg = 0x00003801, .div = 0x7},
108 {.rate = 65000000, .cfg = 0x00002c01, .div = 0x4},
109 {.rate = 78750000, .cfg = 0x00002400, .div = 0x7},
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| /arch/arm/mach-ep93xx/ |
| D | clock.c | 32 unsigned long rate; member
39 int (*set_rate)(struct clk *clk, unsigned long rate);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
51 .rate = EP93XX_EXT_CLK_RATE,
110 .rate = EP93XX_EXT_CLK_RATE,
114 .rate = EP93XX_EXT_CLK_RATE,
315 unsigned long rate = clk_get_rate(clk->parent); in get_uart_rate() local
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| /arch/c6x/platforms/ |
| D | pll.c | 81 return clk->rate; in clk_get_rate()
85 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
91 return clk->round_rate(clk, rate); in clk_round_rate()
93 return clk->rate; in clk_round_rate()
104 clk->rate = clk->recalc(clk); in propagate_rate()
109 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
118 ret = clk->set_rate(clk, rate); in clk_set_rate()
123 clk->rate = clk->recalc(clk); in clk_set_rate()
151 clk->rate = clk->recalc(clk); in clk_set_parent()
164 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| /arch/blackfin/mach-bf609/ |
| D | clock.c | 119 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
123 ret = clk->ops->round_rate(clk, rate); in clk_round_rate()
128 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
132 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
139 return clk->rate; in vco_get_rate()
152 clk->parent->rate = clk_get_rate(clk->parent); in pll_get_rate()
153 return clk->parent->rate / (df + 1) * msel * 2; in pll_get_rate()
156 unsigned long pll_round_rate(struct clk *clk, unsigned long rate) in pll_round_rate() argument
159 div = rate / clk->parent->rate; in pll_round_rate()
160 return clk->parent->rate * div; in pll_round_rate()
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| /arch/mips/lantiq/ |
| D | clk.c | 34 cpu_clk_generic[0].rate = cpu; in clkdev_add_static()
35 cpu_clk_generic[1].rate = fpi; in clkdev_add_static()
36 cpu_clk_generic[2].rate = io; in clkdev_add_static()
37 cpu_clk_generic[3].rate = ppe; in clkdev_add_static()
72 if (clk->rate != 0) in clk_get_rate()
73 return clk->rate; in clk_get_rate()
82 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
89 while (*r && (*r != rate)) in clk_set_rate()
93 clk->cl.dev_id, clk->cl.con_id, rate); in clk_set_rate()
97 clk->rate = rate; in clk_set_rate()
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| /arch/sh/kernel/cpu/sh4/ |
| D | clock-sh4-202.c | 28 return clk->parent->rate / frqcr3_divisors[idx]; in emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) in frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; in frqcr3_lookup()
56 return clk->parent->rate / frqcr3_divisors[idx]; in femi_clk_recalc()
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
94 return clk->parent->rate / frqcr3_divisors[idx]; in shoc_clk_recalc()
97 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) in shoc_clk_verify_rate() argument
104 if (rate > bclk_rate) in shoc_clk_verify_rate()
106 if (rate > 66000000) in shoc_clk_verify_rate()
112 static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) in shoc_clk_set_rate() argument
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| D | clock-sh4.c | 31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
41 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
51 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
61 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /arch/arm/mach-omap1/ |
| D | clock.c | 57 return clk->parent->rate / div; in omap1_sossi_recalc()
135 static int calc_dsor_exp(struct clk *clk, unsigned long rate) in calc_dsor_exp() argument
156 realrate = parent->rate; in calc_dsor_exp()
158 if (realrate <= rate) in calc_dsor_exp()
172 return clk->parent->rate / dsor; in omap1_ckctl_recalc()
190 return clk->parent->rate / dsor; in omap1_ckctl_recalc_dsp_domain()
194 int omap1_select_table_rate(struct clk *clk, unsigned long rate) in omap1_select_table_rate() argument
200 ref_rate = ck_ref_p->rate; in omap1_select_table_rate()
202 for (ptr = omap1_rate_table; ptr->rate; ptr++) { in omap1_select_table_rate()
210 if (ptr->rate <= rate) in omap1_select_table_rate()
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| D | clock.h | 50 #define __clk_get_rate(clk) (clk->rate)
148 unsigned long rate; member
168 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
169 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
198 extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
199 extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
201 extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
204 extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
205 extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
207 extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
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| D | time.c | 164 static __init void omap_init_mpu_timer(unsigned long rate) in omap_init_mpu_timer() argument
167 omap_mpu_timer_start(0, (rate / HZ) - 1, 1); in omap_init_mpu_timer()
170 clockevents_config_and_register(&clockevent_mpu_timer1, rate, in omap_init_mpu_timer()
186 static void __init omap_init_clocksource(unsigned long rate) in omap_init_clocksource() argument
193 sched_clock_register(omap_mpu_read_sched_clock, 32, rate); in omap_init_clocksource()
195 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, in omap_init_clocksource()
203 unsigned long rate; in omap_mpu_timer_init() local
207 rate = clk_get_rate(ck_ref); in omap_mpu_timer_init()
211 rate /= 2; in omap_mpu_timer_init()
213 omap_init_mpu_timer(rate); in omap_mpu_timer_init()
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| D | clock_data.c | 81 .rate = 12000000,
423 .rate = 12000000,
443 .rate = 48000000,
462 .rate = 12000000,
481 .rate = 12000000,
501 .rate = 48000000,
513 .rate = 6000000,
523 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
533 .rate = 48000000,
544 .rate = 48000000,
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| /arch/arm/mach-davinci/ |
| D | clock.c | 131 return clk->rate; in clk_get_rate()
135 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
141 return clk->round_rate(clk, rate); in clk_round_rate()
143 return clk->rate; in clk_round_rate()
154 clk->rate = clk->recalc(clk); in propagate_rate()
159 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
170 ret = clk->set_rate(clk, rate); in clk_set_rate()
175 clk->rate = clk->recalc(clk); in clk_set_rate()
213 clk->rate = clk->recalc(clk); in clk_set_parent()
235 if (WARN(clk->parent && !clk->parent->rate, in clk_register()
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| D | clock.h | 91 unsigned long rate; member
104 int (*set_rate) (struct clk *clk, unsigned long rate);
105 int (*round_rate) (struct clk *clk, unsigned long rate);
131 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
132 int davinci_set_refclk_rate(unsigned long rate);
133 int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
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| /arch/mips/ar7/ |
| D | clock.c | 101 .rate = 125000000,
105 .rate = 150000000,
195 base_clock = cpu_clk.rate; in tnetd7300_get_clock()
222 int base_clock = bus_clk.rate; in tnetd7300_set_clock()
226 base_clock = bus_clk.rate; in tnetd7300_set_clock()
235 base_clock = cpu_clk.rate; in tnetd7300_set_clock()
257 bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
261 cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, in tnetd7300_init_clocks()
264 cpu_clk.rate = bus_clk.rate; in tnetd7300_init_clocks()
266 if (dsp_clk.rate == 250000000) in tnetd7300_init_clocks()
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| /arch/mips/ralink/ |
| D | clk.c | 22 unsigned long rate; member
25 void ralink_clk_add(const char *dev, unsigned long rate) in ralink_clk_add() argument
35 clk->rate = rate; in ralink_clk_add()
59 return clk->rate; in clk_get_rate()
63 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
69 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
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| /arch/arm/mach-omap2/ |
| D | clkt2xxx_dpllcore.c | 111 int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, in omap2_reprogram_dpllcore() argument
123 if ((rate == (cur_rate / 2)) && (mult == 2)) { in omap2_reprogram_dpllcore()
125 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { in omap2_reprogram_dpllcore()
127 } else if (rate != cur_rate) { in omap2_reprogram_dpllcore()
128 valid_rate = omap2_dpllcore_round_rate(rate); in omap2_reprogram_dpllcore()
129 if (valid_rate != rate) in omap2_reprogram_dpllcore()
148 if (rate > low) { in omap2_reprogram_dpllcore()
150 mult = ((rate / 2) / 1000000); in omap2_reprogram_dpllcore()
154 mult = (rate / 1000000); in omap2_reprogram_dpllcore()
163 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ in omap2_reprogram_dpllcore()
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| D | clkt2xxx_virt_prcm_set.c | 74 long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_round_to_table_rate() argument
91 if (ptr->mpu_speed <= rate) in omap2_round_to_table_rate()
98 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
113 if (prcm->mpu_speed <= rate) { in omap2_select_table_rate()
121 rate / 1000000); in omap2_select_table_rate()
176 unsigned long rate; in omap2xxx_clkt_vps_check_bootloader_rates() local
178 rate = omap2xxx_clk_get_core_rate(); in omap2xxx_clkt_vps_check_bootloader_rates()
184 if (prcm->dpll_speed <= rate) in omap2xxx_clkt_vps_check_bootloader_rates()
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| /arch/mips/loongson64/lemote-2f/ |
| D | clock.c | 47 .rate = 800000000,
86 return (unsigned long)clk->rate; in clk_get_rate()
95 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
97 unsigned int rate_khz = rate / 1000; in clk_set_rate()
106 ret = clk->ops->set_rate(clk, rate, 0); in clk_set_rate()
119 clk->rate = rate; in clk_set_rate()
129 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
135 rounded = clk->ops->round_rate(clk, rate); in clk_round_rate()
141 return rate; in clk_round_rate()
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| /arch/arm/mach-mmp/ |
| D | clock.c | 84 unsigned long rate; in clk_get_rate() local
87 rate = clk->ops->getrate(clk); in clk_get_rate()
89 rate = clk->rate; in clk_get_rate()
91 return rate; in clk_get_rate()
95 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
102 ret = clk->ops->setrate(clk, rate); in clk_set_rate()
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| D | clock.h | 22 unsigned long rate; member
33 .rate = _rate, \
41 .rate = _rate, \
49 .rate = _rate, \
57 .rate = _rate, \
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| /arch/arm/mach-w90x900/ |
| D | time.c | 125 unsigned int rate; in nuc900_clockevents_init() local
133 rate = clk_get_rate(clk) / (PRESCALE + 1); in nuc900_clockevents_init()
135 timer0_load = (rate / TICKS_PER_SEC); in nuc900_clockevents_init()
142 clockevents_config_and_register(&nuc900_clockevent_device, rate, in nuc900_clockevents_init()
149 unsigned int rate; in nuc900_clocksource_init() local
157 rate = clk_get_rate(clk) / (PRESCALE + 1); in nuc900_clocksource_init()
165 clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200, in nuc900_clocksource_init()
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| /arch/sh/kernel/cpu/sh3/ |
| D | clock-sh7710.c | 29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
39 return clk->parent->rate / md_table[idx]; in module_clk_recalc()
49 return clk->parent->rate / md_table[idx]; in bus_clk_recalc()
59 return clk->parent->rate / md_table[idx]; in cpu_clk_recalc()
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| D | clock-sh7705.c | 35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
45 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
55 return clk->parent->rate / stc_multipliers[idx]; in bus_clk_recalc()
65 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7770.c | 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; in master_clk_init()
34 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 return clk->parent->rate / bfc_divisors[idx]; in bus_clk_recalc()
54 return clk->parent->rate / ifc_divisors[idx]; in cpu_clk_recalc()
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| /arch/mips/kernel/ |
| D | cevt-ds1287.c | 35 u8 rate; in ds1287_set_base_clock() local
39 rate = 0x9; in ds1287_set_base_clock()
42 rate = 0x8; in ds1287_set_base_clock()
45 rate = 0x6; in ds1287_set_base_clock()
51 CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A); in ds1287_set_base_clock()
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