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Searched refs:readl_relaxed (Results 1 – 25 of 95) sorted by relevance

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/arch/arm/mach-mv78xx0/
Dirq.c34 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_LOW_OFF); in mv78xx0_legacy_handle_irq()
35 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_LOW_OFF); in mv78xx0_legacy_handle_irq()
41 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_HIGH_OFF); in mv78xx0_legacy_handle_irq()
42 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_HIGH_OFF); in mv78xx0_legacy_handle_irq()
48 stat = readl_relaxed(mv78xx0_irq_base + IRQ_CAUSE_ERR_OFF); in mv78xx0_legacy_handle_irq()
49 stat &= readl_relaxed(mv78xx0_irq_base + IRQ_MASK_ERR_OFF); in mv78xx0_legacy_handle_irq()
/arch/arm/mach-zx/
Dzx296702-pm-domain.c44 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); in normal_power_off()
49 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); in normal_power_off()
54 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); in normal_power_off()
59 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); in normal_power_off()
63 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); in normal_power_off()
80 tmp = readl_relaxed(pcubase + PCU_DM_PWRDN); in normal_power_on()
84 tmp = readl_relaxed(pcubase + PCU_DM_ACK_SYNC) & BIT(zpd->bit); in normal_power_on()
92 tmp = readl_relaxed(pcubase + PCU_DM_RSTEN); in normal_power_on()
97 tmp = readl_relaxed(pcubase + PCU_DM_ISOEN); in normal_power_on()
102 tmp = readl_relaxed(pcubase + PCU_DM_CLKEN); in normal_power_on()
/arch/arm/mach-dove/
Dirq.c47 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); in dove_legacy_handle_irq()
48 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); in dove_legacy_handle_irq()
54 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); in dove_legacy_handle_irq()
55 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); in dove_legacy_handle_irq()
/arch/arm/plat-samsung/
Dcpu.c32 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118); in s3c64xx_init_cpu()
39 samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); in s3c64xx_init_cpu()
49 samsung_cpu_id = readl_relaxed(cpuid_addr); in s5p_init_cpu()
Dpm-common.c34 ptr->val = readl_relaxed(ptr->reg); in s3c_pm_do_save()
54 ptr->reg, ptr->val, readl_relaxed(ptr->reg)); in s3c_pm_do_restore()
/arch/arm/mach-hisi/
Dhotplug.c108 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
118 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
204 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
209 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
214 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
220 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
241 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
248 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
Dplatmcpm.c90 data = readl_relaxed(fabric + FAB_SF_MODE); in hip04_set_snoop_filter()
98 } while (data != readl_relaxed(fabric + FAB_SF_MODE)); in hip04_set_snoop_filter()
128 data = readl_relaxed(sys_status); in hip04_boot_secondary()
138 } while (data == readl_relaxed(sys_status)); in hip04_boot_secondary()
211 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_cpu_kill()
226 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_cpu_kill()
/arch/arm/mach-vexpress/
Ddcscb.c49 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerup()
64 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerup()
78 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerdown_prepare()
90 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerdown_prepare()
151 cfg = readl_relaxed(dcscb_base + DCS_CFG_R); in dcscb_init()
Dtc2_pm.c123 return !(readl_relaxed(scc + RESET_CTRL) & mask); in tc2_core_in_reset()
139 readl_relaxed(scc + RESET_CTRL)); in tc2_pm_wait_for_powerdown()
223 a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; in tc2_pm_init()
224 a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; in tc2_pm_init()
228 sys_info = readl_relaxed(scc + SYS_INFO); in tc2_pm_init()
/arch/arm/plat-omap/
Dcounter_32k.c43 return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_32k_read_sched_clock()
63 cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_read_persistent_clock64()
92 if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & in omap_init_clocksource_32k()
/arch/arm/kernel/
Dsmp_scu.c33 unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); in scu_get_core_count()
47 scu_ctrl = readl_relaxed(scu_base + 0x30); in scu_enable()
53 scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); in scu_enable()
Dio.c21 value = readl_relaxed(reg) & ~mask; in atomic_io_modify_relaxed()
34 value = readl_relaxed(reg) & ~mask; in atomic_io_modify()
/arch/arm/mach-sa1100/include/mach/
Dmtd-xip.h23 #define xip_currtime() readl_relaxed(OSCR)
24 #define xip_elapsed_since(x) (signed)((readl_relaxed(OSCR) - (x)) / 4)
/arch/arm/mach-omap2/
Domap4-common.c123 writel_relaxed(readl_relaxed(dram_sync), dram_sync); in omap_interconnect_sync()
124 writel_relaxed(readl_relaxed(sram_sync), sram_sync); in omap_interconnect_sync()
192 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); in gic_dist_disabled()
197 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
198 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); in gic_timer_retrigger()
199 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
Domap-wakeupgen.c77 return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_readl()
233 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap4_irq_save_context()
235 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); in omap4_irq_save_context()
239 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); in omap4_irq_save_context()
241 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); in omap4_irq_save_context()
245 val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); in omap4_irq_save_context()
266 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
268 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
272 val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); in omap5_irq_save_context()
320 val = readl_relaxed(sar_base + offset); in irq_sar_clear()
Dwd_timer.c53 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
57 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
/arch/arm/mach-ks8695/
Dtime.c64 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_periodic()
86 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_next_event()
133 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_timer_setup()
164 reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_restart()
/arch/arm/mach-imx/
Dsrc.c61 val = readl_relaxed(src_base + SRC_SCR); in imx_src_reset_module()
92 val = readl_relaxed(src_base + SRC_SCR); in imx_enable_cpu()
109 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); in imx_get_cpu_arg()
138 val = readl_relaxed(src_base + SRC_SCR); in imx_src_init()
Dpm-imx6.c222 u32 val = readl_relaxed(ccm_base + CGPR); in imx6_set_int_mem_clk_lpm()
241 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
247 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
268 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
274 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
282 u32 val = readl_relaxed(ccm_base + CLPCR); in imx6_set_lpm()
554 readl_relaxed(pm_info->iomuxc_base.vbase + in imx6q_suspend_init()
642 val = readl_relaxed(ccm_base + CLPCR); in imx6_pm_ccm_init()
Dsystem.c109 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { in imx_init_l2cache()
111 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); in imx_init_l2cache()
/arch/arm/mach-orion5x/
Dirq.c34 stat = readl_relaxed(MAIN_IRQ_CAUSE); in orion5x_legacy_handle_irq()
35 stat &= readl_relaxed(MAIN_IRQ_MASK); in orion5x_legacy_handle_irq()
/arch/arm/mach-omap1/
Dirq.c72 return readl_relaxed(irq_banks[bank].va + offset); in irq_bank_readl()
151 irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); in omap1_handle_irq()
152 irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); in omap1_handle_irq()
156 irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); in omap1_handle_irq()
160 irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); in omap1_handle_irq()
162 irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); in omap1_handle_irq()
/arch/arm/mm/
Dcache-l2x0.c69 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
79 if (val == readl_relaxed(base + reg)) in l2c_write_sec()
157 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); in l2c_save()
165 if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) in l2c_resume()
412 if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN) in l2c220_unlock()
557 l2x0_saved_regs.tag_latency = readl_relaxed(base + in l2c310_save()
559 l2x0_saved_regs.data_latency = readl_relaxed(base + in l2c310_save()
561 l2x0_saved_regs.filter_end = readl_relaxed(base + in l2c310_save()
563 l2x0_saved_regs.filter_start = readl_relaxed(base + in l2c310_save()
566 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_save()
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/arch/arm/mach-ux500/
Dpm.c98 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); in prcmu_gic_pending_irq()
99 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in prcmu_gic_pending_irq()
151 er = readl_relaxed(dist_base + in prcmu_copy_gic_settings()
/arch/arm/mach-mmp/
Ddevices.c85 return readl_relaxed(base + offset); in u2o_get()
93 reg = readl_relaxed(base + offset); in u2o_set()
96 readl_relaxed(base + offset); in u2o_set()
104 reg = readl_relaxed(base + offset); in u2o_clear()
107 readl_relaxed(base + offset); in u2o_clear()
114 readl_relaxed(base + offset); in u2o_write()

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