/arch/arm/kernel/ |
D | smp_scu.c | 31 unsigned int __init scu_get_core_count(void __iomem *scu_base) in scu_get_core_count() argument 33 unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); in scu_get_core_count() 40 void scu_enable(void __iomem *scu_base) in scu_enable() argument 47 scu_ctrl = readl_relaxed(scu_base + 0x30); in scu_enable() 49 writel_relaxed(scu_ctrl | 0x1, scu_base + 0x30); in scu_enable() 53 scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); in scu_enable() 65 writel_relaxed(scu_ctrl, scu_base + SCU_CTRL); in scu_enable() 83 int scu_power_mode(void __iomem *scu_base, unsigned int mode) in scu_power_mode() argument 91 val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; in scu_power_mode() 93 writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); in scu_power_mode()
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/arch/arm/mach-realview/ |
D | platsmp-dt.c | 42 void __iomem *scu_base; in realview_smp_prepare_cpus() local 52 scu_base = of_iomap(np, 0); in realview_smp_prepare_cpus() 54 if (!scu_base) { in realview_smp_prepare_cpus() 59 scu_enable(scu_base); in realview_smp_prepare_cpus() 60 ncores = scu_get_core_count(scu_base); in realview_smp_prepare_cpus() 64 iounmap(scu_base); in realview_smp_prepare_cpus()
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/arch/arm/mach-ux500/ |
D | platsmp.c | 37 static void __iomem *scu_base; in ux500_smp_prepare_cpus() local 58 scu_base = of_iomap(np, 0); in ux500_smp_prepare_cpus() 60 if (!scu_base) { in ux500_smp_prepare_cpus() 65 scu_enable(scu_base); in ux500_smp_prepare_cpus() 66 ncores = scu_get_core_count(scu_base); in ux500_smp_prepare_cpus() 69 iounmap(scu_base); in ux500_smp_prepare_cpus()
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/arch/arm/mach-bcm/ |
D | bcm63xx_smp.c | 39 void __iomem *scu_base; in scu_a9_enable() local 54 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable() 55 if (!scu_base) { in scu_a9_enable() 61 scu_enable(scu_base); in scu_a9_enable() 63 ncores = scu_base ? scu_get_core_count(scu_base) : 1; in scu_a9_enable() 95 iounmap(scu_base); /* That's the last we'll need of this */ in scu_a9_enable()
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D | platsmp.c | 55 void __iomem *scu_base; in scu_a9_enable() local 69 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable() 70 if (!scu_base) { in scu_a9_enable() 76 scu_enable(scu_base); in scu_a9_enable() 78 iounmap(scu_base); /* That's the last we'll need of this */ in scu_a9_enable()
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/arch/arm/include/asm/ |
D | smp_scu.h | 32 static inline unsigned int scu_get_core_count(void __iomem *scu_base) in scu_get_core_count() argument 36 static inline int scu_power_mode(void __iomem *scu_base, unsigned int mode) in scu_power_mode() argument 43 void scu_enable(void __iomem *scu_base); 45 static inline void scu_enable(void __iomem *scu_base) {} in scu_enable() argument
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/arch/arm/mach-oxnas/ |
D | platsmp.c | 66 void __iomem *scu_base; in ox820_smp_prepare_cpus() local 69 scu_base = of_iomap(np, 0); in ox820_smp_prepare_cpus() 71 if (!scu_base) in ox820_smp_prepare_cpus() 87 scu_enable(scu_base); in ox820_smp_prepare_cpus() 91 iounmap(scu_base); in ox820_smp_prepare_cpus()
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/arch/arm/mach-zx/ |
D | platsmp.c | 42 static void __iomem *scu_base; variable 52 scu_base = ioremap(base, SZ_256); in zx_smp_prepare_cpus() 53 if (!scu_base) { in zx_smp_prepare_cpus() 58 scu_enable(scu_base); in zx_smp_prepare_cpus() 166 scu_power_mode(scu_base, SCU_PM_POWEROFF); in zx_cpu_die() 176 scu_power_mode(scu_base, SCU_PM_NORMAL); in zx_secondary_init()
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/arch/arm/mach-berlin/ |
D | platsmp.c | 64 void __iomem *scu_base; in berlin_smp_prepare_cpus() local 68 scu_base = of_iomap(np, 0); in berlin_smp_prepare_cpus() 70 if (!scu_base) in berlin_smp_prepare_cpus() 83 scu_enable(scu_base); in berlin_smp_prepare_cpus() 100 iounmap(scu_base); in berlin_smp_prepare_cpus()
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/arch/arm/mach-imx/ |
D | platsmp.c | 27 static void __iomem *scu_base; variable 46 scu_base = IMX_IO_ADDRESS(base); in imx_scu_map_io() 64 ncores = scu_get_core_count(scu_base); in imx_smp_init_cpus() 72 scu_enable(scu_base); in imx_smp_prepare()
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/arch/arm/mach-omap2/ |
D | omap-smp.c | 50 void __iomem *scu_base; member 76 return cfg.scu_base; in omap4_get_scu_base() 293 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); in omap4_smp_init_cpus() 294 BUG_ON(!cfg.scu_base); in omap4_smp_init_cpus() 295 ncores = scu_get_core_count(cfg.scu_base); in omap4_smp_init_cpus() 413 if (cfg.scu_base) in omap4_smp_prepare_cpus() 414 scu_enable(cfg.scu_base); in omap4_smp_prepare_cpus()
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/arch/arm/mach-hisi/ |
D | platsmp.c | 45 void __iomem *scu_base = NULL; in hisi_enable_scu_a9() local 49 scu_base = ioremap(base, SZ_4K); in hisi_enable_scu_a9() 50 if (!scu_base) { in hisi_enable_scu_a9() 54 scu_enable(scu_base); in hisi_enable_scu_a9() 55 iounmap(scu_base); in hisi_enable_scu_a9()
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/arch/arm/mach-spear/ |
D | platsmp.c | 37 static void __iomem *scu_base = IOMEM(VA_SCU_BASE); variable 98 unsigned int i, ncores = scu_get_core_count(scu_base); in spear13xx_smp_init_cpus() 113 scu_enable(scu_base); in spear13xx_smp_prepare_cpus()
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/arch/arm/mach-mvebu/ |
D | board-v7.c | 36 static void __iomem *scu_base; variable 47 scu_base = of_iomap(np, 0); in mvebu_scu_enable() 48 scu_enable(scu_base); in mvebu_scu_enable() 55 return scu_base; in mvebu_get_scu_base()
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/arch/arm/mach-sti/ |
D | platsmp.c | 102 void __iomem *scu_base; in sti_smp_prepare_cpus() local 111 scu_base = of_iomap(np, 0); in sti_smp_prepare_cpus() 112 scu_enable(scu_base); in sti_smp_prepare_cpus()
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