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Searched refs:slice (Results 1 – 24 of 24) sorted by relevance

/arch/mips/sgi-ip27/
Dip27-nmi.c36 void install_cpu_nmi_handler(int slice) in install_cpu_nmi_handler() argument
40 nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice); in install_cpu_nmi_handler()
55 void nmi_cpu_eframe_save(nasid_t nasid, int slice) in nmi_cpu_eframe_save() argument
63 slice * IP27_NMI_KREGS_CPU_SIZE); in nmi_cpu_eframe_save()
65 printk("NMI nasid %d: slice %d\n", nasid, slice); in nmi_cpu_eframe_save()
131 void nmi_dump_hub_irq(nasid_t nasid, int slice) in nmi_dump_hub_irq() argument
135 if (slice == 0) { /* Slice A */ in nmi_dump_hub_irq()
158 int slice; in nmi_node_eframe_save() local
169 for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) { in nmi_node_eframe_save()
170 nmi_cpu_eframe_save(nasid, slice); in nmi_node_eframe_save()
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Dip27-klconfig.c81 klcpu_t *nasid_slice_to_cpuinfo(nasid_t nasid, int slice) in nasid_slice_to_cpuinfo() argument
93 if ((acpu->cpu_info.physid) == slice) in nasid_slice_to_cpuinfo()
103 int slice; in sn_get_cpuinfo() local
120 for (slice = 0; slice < CPUS_PER_NODE; slice++) { in sn_get_cpuinfo()
121 acpu = nasid_slice_to_cpuinfo(nasid, slice); in sn_get_cpuinfo()
Dip27-init.c116 int slice = LOCAL_HUB_L(PI_CPU_NUM); in per_cpu_init() local
119 struct slice_data *si = hub->slice + slice; in per_cpu_init()
122 if (test_and_set_bit(slice, &hub->slice_map)) in per_cpu_init()
Dip27-irq.c190 int slice = LOCAL_HUB_L(PI_CPU_NUM); in install_ipi() local
196 resched = CPU_RESCHED_A_IRQ + slice; in install_ipi()
201 call = CPU_CALL_A_IRQ + slice; in install_ipi()
206 if (slice == 0) { in install_ipi()
Dip27-timer.c58 int slice = cputoslice(cpu); in rt_next_event() local
63 LOCAL_HUB_S(PI_RT_COMPARE_A + PI_COUNT_OFFSET * slice, cnt); in rt_next_event()
77 int slice = cputoslice(cpu); in hub_rt_counter_handler() local
82 LOCAL_HUB_S(PI_RT_PEND_A + PI_COUNT_OFFSET * slice, 0); in hub_rt_counter_handler()
/arch/mips/include/asm/sn/
Daddrs.h302 #define EX_HANDLER_OFFSET(slice) ((slice) << 16) argument
303 #define EX_HANDLER_ADDR(nasid, slice) \ argument
304 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
307 #define EX_FRAME_OFFSET(slice) ((slice) << 16 | 0x400) argument
308 #define EX_FRAME_ADDR(nasid, slice) \ argument
309 PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
356 #define LAUNCH_OFFSET(nasid, slice) \ argument
358 KLD_LAUNCH(nasid)->stride * (slice))
359 #define LAUNCH_ADDR(nasid, slice) \ argument
360 TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
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Dsn_private.h14 extern void install_cpu_nmi_handler(int slice);
/arch/ia64/include/asm/sn/
Dsn_cpuid.h96 #define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
106 #define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
Dnodepda.h34 char slice; member
Dgeo.h56 char slice; /* Which CPU on the node */ member
Dsn_sal.h1006 ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice) in ia64_sn_get_sapic_info() argument
1020 if (slice) *slice = (sapicid >> 12) & 3; in ia64_sn_get_sapic_info()
1030 if (slice) *slice = (int) ret_stuff.v2; in ia64_sn_get_sapic_info()
/arch/powerpc/mm/
Dslice.c108 static int slice_low_has_vma(struct mm_struct *mm, unsigned long slice) in slice_low_has_vma() argument
110 return !slice_area_is_free(mm, slice << SLICE_LOW_SHIFT, in slice_low_has_vma()
114 static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice) in slice_high_has_vma() argument
116 unsigned long start = slice << SLICE_HIGH_SHIFT; in slice_high_has_vma()
265 unsigned long slice; in slice_scan_available() local
267 slice = GET_LOW_SLICE_INDEX(addr); in slice_scan_available()
268 *boundary_addr = (slice + end) << SLICE_LOW_SHIFT; in slice_scan_available()
269 return !!(available.low_slices & (1u << slice)); in slice_scan_available()
271 slice = GET_HIGH_SLICE_INDEX(addr); in slice_scan_available()
272 *boundary_addr = (slice + end) ? in slice_scan_available()
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DMakefile32 obj-$(CONFIG_PPC_MM_SLICES) += slice.o
/arch/ia64/sn/kernel/
Dirq.c116 nasid_t nasid, int slice) in sn_retarget_vector() argument
143 status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice); in sn_retarget_vector()
165 nasid, slice); in sn_retarget_vector()
210 int slice; in sn_set_affinity_irq() local
213 slice = cpuid_to_slice(cpumask_first_and(mask, cpu_online_mask)); in sn_set_affinity_irq()
217 (void)sn_retarget_vector(sn_irq_info, nasid, slice); in sn_set_affinity_irq()
341 int slice = sn_irq_info->irq_slice; in sn_irq_fixup() local
342 int cpu = nasid_slice_to_cpuid(nasid, slice); in sn_irq_fixup()
Dsetup.c567 int slice; in sn_cpu_init() local
619 if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice)) in sn_cpu_init()
625 nodepdaindr[i]->phys_cpuid[cpuid].slice = slice; in sn_cpu_init()
635 (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT)); in sn_cpu_init()
672 (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]); in sn_cpu_init()
748 nasid_slice_to_cpuid(int nasid, int slice) in nasid_slice_to_cpuid() argument
754 cpuid_to_slice(cpu) == slice) in nasid_slice_to_cpuid()
Dmsi_sn.c159 int slice; in sn_set_msi_irq_affinity() local
188 slice = cpuid_to_slice(cpu); in sn_set_msi_irq_affinity()
190 new_irq_info = sn_retarget_vector(sn_irq_info, nasid, slice); in sn_set_msi_irq_affinity()
Dtiocx.c280 nasid_t req_nasid, int slice) in tiocx_irq_alloc() argument
294 req_nasid, slice); in tiocx_irq_alloc()
/arch/mips/include/asm/mach-ip27/
Dmmzone.h24 struct slice_data slice[2]; member
/arch/mips/include/asm/mach-loongson64/
Dmmzone.h37 struct slice_data slice[2]; member
/arch/mips/include/asm/sn/sn0/
Daddrs.h148 #define KERN_NMI_ADDR(nasid, slice) \ argument
150 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
/arch/ia64/sn/kernel/sn2/
Dsn_hwperf.c386 char slice; in sn_topology_show() local
475 slice = 'a' + cpuid_to_slice(i); in sn_topology_show()
479 i, obj->location, slice, in sn_topology_show()
699 char slice; in sn_hwperf_ioctl() local
762 slice = 'a' + cpuid_to_slice(j); in sn_hwperf_ioctl()
773 slice); in sn_hwperf_ioctl()
/arch/sparc/include/asm/
Dvio.h157 u8 slice; member
/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c367 gmxx_tx_spi_max.s.slice = 0; in cvmx_spi_calendar_setup_cb()
/arch/mips/include/asm/octeon/
Dcvmx-gmxx-defs.h6807 uint64_t slice:7; member
6813 uint64_t slice:7;