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/arch/x86/crypto/
Dpoly1305-avx2-x86_64.S62 #define t1 %ymm5 macro
105 vpunpcklqdq t1,ruwy0,ruwy0
108 vpunpcklqdq t2,t1,t1
109 vperm2i128 $0x20,t1,ruwy0,ruwy0
114 vpunpcklqdq t1,ruwy1,ruwy1
117 vpunpcklqdq t2,t1,t1
118 vperm2i128 $0x20,t1,ruwy1,ruwy1
125 vpunpcklqdq t1,ruwy2,ruwy2
128 vpunpcklqdq t2,t1,t1
129 vperm2i128 $0x20,t1,ruwy2,ruwy2
[all …]
Dpoly1305-sse2-x86_64.S42 #define t1 %xmm3 macro
88 movd h1,t1
92 punpcklqdq t1,h01
97 movd 0x00(m),t1
100 punpcklqdq t2,t1
101 pand mask,t1
102 paddd t1,h01
104 movd 0x06(m),t1
106 psrld $4,t1
108 punpcklqdq t2,t1
[all …]
/arch/x86/purgatory/
Dsha256.c50 u32 a, b, c, d, e, f, g, h, t1, t2; in sha256_transform() local
67 t1 = h + e1(e) + Ch(e, f, g) + 0x428a2f98 + W[0]; in sha256_transform()
68 t2 = e0(a) + Maj(a, b, c); d += t1; h = t1 + t2; in sha256_transform()
69 t1 = g + e1(d) + Ch(d, e, f) + 0x71374491 + W[1]; in sha256_transform()
70 t2 = e0(h) + Maj(h, a, b); c += t1; g = t1 + t2; in sha256_transform()
71 t1 = f + e1(c) + Ch(c, d, e) + 0xb5c0fbcf + W[2]; in sha256_transform()
72 t2 = e0(g) + Maj(g, h, a); b += t1; f = t1 + t2; in sha256_transform()
73 t1 = e + e1(b) + Ch(b, c, d) + 0xe9b5dba5 + W[3]; in sha256_transform()
74 t2 = e0(f) + Maj(f, g, h); a += t1; e = t1 + t2; in sha256_transform()
75 t1 = d + e1(a) + Ch(a, b, c) + 0x3956c25b + W[4]; in sha256_transform()
[all …]
/arch/mips/netlogic/common/
Dreset.S60 mfcr t1, t0
63 or t1, t1, t2
64 mtcr t1, t0
67 mfcr t1, t0
68 ori t1, 0x1000 /* Enable Icache partitioning */
69 mtcr t1, t0
72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
73 mtcr t1, t0
83 li t1, (1 << 29) /* ELPA bit */
84 or t0, t1
[all …]
Dsmpboot.S62 PTR_LA t1, nlm_reset_entry
64 dsubu t2, t1
76 move t1, zero
78 ori t1, ST0_KX
80 mtc0 t1, CP0_STATUS
81 PTR_LA t1, nlm_next_sp
82 PTR_L sp, 0(t1)
83 PTR_LA t1, nlm_next_gp
84 PTR_L gp, 0(t1)
111 ADDIU t1, t3, BOOT_CPU_READY
[all …]
/arch/arm/crypto/
Dsha512-armv4.pl67 $t1="r10";
92 mov $t1,$Ehi,lsr#14
96 eor $t1,$t1,$Elo,lsl#18
99 eor $t1,$t1,$Ehi,lsr#18
101 eor $t1,$t1,$Elo,lsl#14
103 eor $t1,$t1,$Elo,lsr#9
105 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
108 adc $Thi,$Thi,$t1 @ T += Sigma1(e)
109 ldr $t1,[sp,#$Foff+4] @ f.hi
117 eor $t1,$t1,$t3
[all …]
Dsha256-armv4.pl45 $len="r2"; $t1="r2";
69 @ ldr $t1,[$inp],#4 @ $i
77 rev $t1,$t1
80 @ ldrb $t1,[$inp,#3] @ $i
84 orr $t1,$t1,$t2,lsl#8
86 orr $t1,$t1,$t0,lsl#16
91 orr $t1,$t1,$t2,lsl#24
97 add $h,$h,$t1 @ h+=X[i]
98 str $t1,[sp,#`$i%16`*4]
99 eor $t1,$f,$g
[all …]
/arch/mips/kernel/
Dr4k_fpu.S47 fpu_save_double a0 t0 t1 # clobbers t1
59 fpu_restore_double a0 t0 t1 # clobbers t1
102 li t1, ST0_CU1
103 or t0, t1
109 li t1, -1 # SNaN
115 dmtc1 t1, $f1
116 dmtc1 t1, $f3
117 dmtc1 t1, $f5
118 dmtc1 t1, $f7
119 dmtc1 t1, $f9
[all …]
Dcps-vec.S183 1: PTR_L t1, VPEBOOTCFG_PC(v1)
186 jr t1
245 PTR_LA t1, 1f
246 jr.hb t1
276 sll t1, ta1, VPECONF0_XTC_SHIFT
277 or t0, t0, t1
314 li t1, COREBOOTCFG_SIZE
315 mul t0, t0, t1
316 PTR_LA t1, mips_cps_core_bootcfg
317 PTR_L t1, 0(t1)
[all …]
Docteon_switch.S27 mfc0 t1, CP0_STATUS
28 LONG_S t1, THREAD_STATUS(a0)
42 li t1, -32768 /* Base address of CVMSEG */
47 LONG_L t8, 0(t1) /* Load from CVMSEG */
49 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
50 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
78 set_saved_sp t0, t1, t2
80 mfc0 t1, CP0_STATUS /* Do we really need this? */
82 and t1, a3
86 or a2, t1
[all …]
Dbmips_5xxx_init.S30 addu t1, kva, size ; \
34 addiu t1, t1, -1 ; \
35 and t1, t2 ; \
37 bne t0, t1, 9b ; \
421 li t1, 0x4
422 or t0, t1
427 li t1, 0x4
428 or t0, t1
433 li t1, 0x4
434 or t0, t1
[all …]
Dr2300_switch.S34 mfc0 t1, CP0_STATUS
35 sw t1, THREAD_STATUS(a0)
52 addiu t1, $28, _THREAD_SIZE - 32
53 sw t1, kernelsp
55 mfc0 t1, CP0_STATUS /* Do we really need this? */
57 and t1, a3
61 or a2, t1
/arch/mips/include/asm/sibyte/
Dboard.h42 #define setleds(t0, t1, c0, c1, c2, c3) \
44 li t1, c0; \
45 sb t1, 0x18(t0); \
46 li t1, c1; \
47 sb t1, 0x10(t0); \
48 li t1, c2; \
49 sb t1, 0x08(t0); \
50 li t1, c3; \
51 sb t1, 0x00(t0)
53 #define setleds(t0, t1, c0, c1, c2, c3)
/arch/alpha/lib/
Dstxcpy.S49 mskqh t1, a1, t3 # e0 :
50 ornot t1, t2, t2 # .. e1 :
53 or t0, t3, t1 # e0 :
61 stq_u t1, 0(a0) # e0 :
63 ldq_u t1, 0(a1) # e0 :
65 cmpbge zero, t1, t8 # e0 (stall)
85 zapnot t1, t6, t1 # e0 : clear src bytes >= null
88 or t0, t1, t1 # e1 :
90 1: stq_u t1, 0(a0) # e0 :
109 ldq_u t1, 0(a1) # e0 : load first src word
[all …]
Dev6-stxcpy.S60 mskqh t1, a1, t3 # U :
61 ornot t1, t2, t2 # E : (stall)
65 or t0, t3, t1 # E : (stall)
74 stq_u t1, 0(a0) # L :
79 ldq_u t1, 0(a1) # L : Latency=3
81 cmpbge zero, t1, t8 # E : (3 cycle stall)
100 zapnot t1, t6, t1 # U : clear src bytes >= null (stall)
104 or t0, t1, t1 # E : (stall)
108 1: stq_u t1, 0(a0) # L :
129 ldq_u t1, 0(a1) # L : load first src word
[all …]
Dstxncpy.S57 mskqh t1, a1, t3 # e0 :
58 ornot t1, t2, t2 # .. e1 :
96 ldq_u t1, 0(a0) # e0 :
101 zap t1, t8, t1 # .. e1 : clear dst bytes <= null
102 or t0, t1, t0 # e1 :
122 xor a0, a1, t1 # e0 :
124 and t1, 7, t1 # e0 :
131 bne t1, $unaligned # .. e1 :
135 ldq_u t1, 0(a1) # e0 : load first src word
162 or t1, t4, t1 # e1 : first aligned src word complete
[all …]
Dstrrchr.S33 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
39 andnot t1, t4, t1 # .. e1 : clear garbage from null test
41 bne t1, $eos # .. e1 : did we already hit the terminator?
50 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
52 beq t1, $loop # .. e1 : if we havnt seen a null, loop
56 negq t1, t4 # e0 : isolate first null byte match
57 and t1, t4, t4 # e1 :
74 and t8, 0xcc, t1 # .. e1 :
75 cmovne t1, t1, t8 # e0 :
76 cmovne t1, 2, t1 # .. e1 :
[all …]
/arch/mips/include/asm/mach-paravirt/
Dkernel-entry-init.h32 slti t1, t0, NR_CPUS
33 bnez t1, 1f
39 PTR_LA t1, paravirt_smp_sp
41 PTR_ADDU t1, t1, t0
43 PTR_L sp, 0(t1)
46 PTR_LA t1, paravirt_smp_gp
47 PTR_ADDU t1, t1, t0
49 PTR_L gp, 0(t1)
/arch/mips/dec/
Dint-handler.S133 mfc0 t1,CP0_STATUS
138 and t0,t1 # isolate allowed ones
150 # open coded PTR_LA t1, cpu_mask_nr_tbl
152 # open coded la t1, cpu_mask_nr_tbl
153 lui t1, %hi(cpu_mask_nr_tbl)
154 addiu t1, %lo(cpu_mask_nr_tbl)
214 2: lw t2,(t1)
218 addu t1,2*PTRSIZE # delay slot
223 lw a0,%lo(-PTRSIZE)(t1)
239 li t1,CAUSEF_IP>>CAUSEB_IP # mask
[all …]
/arch/mips/net/
Dbpf_jit_asm.S63 PTR_ADDU t1, $r_skb_data, offset
65 lw $r_A, 0(t1)
73 srl t1, $r_A, 24
75 or t0, t0, t1
77 andi t1, $r_A, 0xff00
79 sll t1, t1, 8
80 or $r_A, t0, t1
92 PTR_ADDU t1, $r_skb_data, offset
93 lhu $r_A, 0(t1)
99 srl t1, $r_A, 8
[all …]
/arch/alpha/include/uapi/asm/
Dswab.h27 __u64 t0, t1, t2, t3; in __arch_swab32() local
30 t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */ in __arch_swab32()
31 t1 |= t0; /* t1 : 000000CCDDAABBCC */ in __arch_swab32()
32 t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */ in __arch_swab32()
33 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */ in __arch_swab32()
35 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */ in __arch_swab32()
37 return t1; in __arch_swab32()
/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h47 and t1, v1, 0xfff8
48 xor t1, t1, 0x9000 # 63-P1
49 beqz t1, 4f
50 and t1, v1, 0xfff8
51 xor t1, t1, 0x9008 # 63-P2
52 beqz t1, 4f
53 and t1, v1, 0xfff8
54 xor t1, t1, 0x9100 # 68-P1
55 beqz t1, 4f
56 and t1, v1, 0xff00
[all …]
/arch/mips/include/asm/mach-ip27/
Dkernel-entry-init.h47 dsll t1, NASID_SHFT # Shift text nasid into place
49 or t1, t1, t0 # Physical load address of kernel text
51 dsrl t1, 12 # 4K pfn
53 dsll t1, 6 # Get pfn into place
56 or t0, t0, t1
78 GET_NASID_ASM t1
79 move t2, t1 # text and data are here
87 GET_NASID_ASM t1
90 dsll t1, NASID_SHFT
91 or t0, t0, t1
[all …]
/arch/parisc/lib/
Dlusercopy.S171 t1 = r19 define
179 a1 = t1
201 extru t0,31,2,t1
202 cmpib,<>,n 0,t1,.Lunaligned_copy
206 extru t0,31,3,t1
207 cmpib,<>,n 0,t1,.Lalign_loop32
211 extru dst,31,3,t1
212 cmpib,=,n 0,t1,.Lcopy_loop_16_start
213 20: ldb,ma 1(srcspc,src),t1
214 21: stb,ma t1,1(dstspc,dst)
[all …]
/arch/mips/include/asm/
Dpm.h69 la t1, mips_static_suspend_state
80 LONG_S k0, SSS_SEGCTL0(t1)
82 LONG_S k0, SSS_SEGCTL1(t1)
84 LONG_S k0, SSS_SEGCTL2(t1)
87 LONG_S sp, SSS_SP(t1)
98 LONG_L k0, SSS_SEGCTL0(t1)
100 LONG_L k0, SSS_SEGCTL1(t1)
102 LONG_L k0, SSS_SEGCTL2(t1)
107 LONG_L sp, SSS_SP(t1)
115 la t1, __wback_cache_all
[all …]

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