| /arch/arm/mach-dove/ |
| D | common.c | 75 static struct clk *tclk; variable
91 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, dove_tclk); in dove_clk_init()
112 orion_clkdev_add(NULL, "orion_spi.0", tclk); in dove_clk_init()
113 orion_clkdev_add(NULL, "orion_spi.1", tclk); in dove_clk_init()
114 orion_clkdev_add(NULL, "orion_wdt", tclk); in dove_clk_init()
115 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk); in dove_clk_init()
185 IRQ_DOVE_UART_0, tclk); in dove_uart0_init()
194 IRQ_DOVE_UART_1, tclk); in dove_uart1_init()
203 IRQ_DOVE_UART_2, tclk); in dove_uart2_init()
212 IRQ_DOVE_UART_3, tclk); in dove_uart3_init()
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| /arch/arm/plat-orion/ |
| D | time.c | 203 unsigned int irq, unsigned int tclk) in orion_time_init() argument
213 ticks_per_jiffy = (tclk + HZ/2) / HZ; in orion_time_init()
215 orion_delay_timer.freq = tclk; in orion_time_init()
221 sched_clock_register(orion_read_sched_clock, 32, tclk); in orion_time_init()
234 tclk, 300, 32, clocksource_mmio_readl_down); in orion_time_init()
241 clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); in orion_time_init()
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| D | common.c | 38 void __init orion_clkdev_init(struct clk *tclk) in orion_clkdev_init() argument
40 orion_clkdev_add(NULL, "orion_spi.0", tclk); in orion_clkdev_init()
41 orion_clkdev_add(NULL, "orion_spi.1", tclk); in orion_clkdev_init()
42 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk); in orion_clkdev_init()
43 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk); in orion_clkdev_init()
44 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk); in orion_clkdev_init()
45 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk); in orion_clkdev_init()
46 orion_clkdev_add(NULL, "orion_wdt", tclk); in orion_clkdev_init()
47 orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk); in orion_clkdev_init()
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| /arch/arm/mach-mv78xx0/ |
| D | common.c | 167 static struct clk *tclk; variable
171 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, get_tclk()); in clk_init()
173 orion_clkdev_init(tclk); in clk_init()
293 IRQ_MV78XX0_UART_0, tclk); in mv78xx0_uart0_init()
303 IRQ_MV78XX0_UART_1, tclk); in mv78xx0_uart1_init()
313 IRQ_MV78XX0_UART_2, tclk); in mv78xx0_uart2_init()
322 IRQ_MV78XX0_UART_3, tclk); in mv78xx0_uart3_init()
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| /arch/arm/mach-orion5x/ |
| D | common.c | 65 static struct clk *tclk; variable
69 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, 0, orion5x_tclk); in clk_init()
71 orion_clkdev_init(tclk); in clk_init()
148 IRQ_ORION5X_UART0, tclk); in orion5x_uart0_init()
157 IRQ_ORION5X_UART1, tclk); in orion5x_uart1_init()
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| /arch/arm/plat-orion/include/plat/ |
| D | time.h | 17 unsigned int irq, unsigned int tclk);
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| D | common.h | 106 void __init orion_clkdev_init(struct clk *tclk);
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| /arch/mips/include/asm/octeon/ |
| D | cvmx-uctlx-defs.h | 439 uint64_t tclk:1; member
447 uint64_t tclk:1;
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| /arch/powerpc/boot/dts/fsl/ |
| D | bsc9131rdb.dtsi | 87 fsl,tclk-period = <5>;
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| D | bsc9132qds.dtsi | 94 fsl,tclk-period = <5>;
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| D | p1022ds.dtsi | 222 fsl,tclk-period = <5>;
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| D | p2020rdb.dts | 230 fsl,tclk-period = <5>;
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| D | p1010rdb.dtsi | 193 fsl,tclk-period = <10>;
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| D | p2020rdb-pc.dtsi | 218 fsl,tclk-period = <5>;
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| D | p1021rdb-pc.dtsi | 231 fsl,tclk-period = <10>;
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| D | p1020rdb-pd.dts | 232 fsl,tclk-period = <10>;
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| D | p2020ds.dtsi | 186 fsl,tclk-period = <5>;
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| D | p1025twr.dtsi | 145 fsl,tclk-period = <10>;
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| D | mpc8572ds.dtsi | 196 fsl,tclk-period = <5>;
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| /arch/arm/mach-omap1/ |
| D | clock.c | 752 void propagate_rate(struct clk *tclk) in propagate_rate() argument
756 list_for_each_entry(clkp, &tclk->children, sibling) { in propagate_rate()
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| /arch/powerpc/boot/dts/ |
| D | mpc8313erdb.dts | 184 fsl,tclk-period = <10>;
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| /arch/arm/boot/dts/ |
| D | am437x-cm-t43.dts | 124 AM4372_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.tclk */
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| D | ls1021a.dtsi | 585 fsl,tclk-period = <5>;
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