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/arch/arm64/crypto/
Dcrc32-ce-core.S126 ld1 {v1.16b-v4.16b}, [BUF], #0x40
129 eor v1.16b, v1.16b, vCONSTANT.16b
139 pmull2 v5.1q, v1.2d, vCONSTANT.2d
144 pmull v1.1q, v1.1d, vCONSTANT.1d
149 eor v1.16b, v1.16b, v5.16b
158 eor v1.16b, v1.16b, v5.16b
169 pmull2 v5.1q, v1.2d, vCONSTANT.2d
170 pmull v1.1q, v1.1d, vCONSTANT.1d
171 eor v1.16b, v1.16b, v5.16b
172 eor v1.16b, v1.16b, v2.16b
[all …]
Daes-ce-ccm-core.S26 eor v1.16b, v1.16b, v1.16b
30 ins v1.b[0], w7
31 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
34 eor v0.16b, v0.16b, v1.16b
61 ld1 {v1.16b}, [x1], #16 /* load next input block */
62 eor v0.16b, v0.16b, v1.16b /* xor with mac */
80 9: ext v1.16b, v1.16b, v1.16b, #1
83 91: eor v0.16b, v0.16b, v1.16b
98 ld1 {v1.16b}, [x1] /* load 1st ctriv */
107 aese v1.16b, v4.16b
[all …]
Daes-ce-core.S17 ld1 {v1.4s}, [x0], #16
21 mov v3.16b, v1.16b
23 0: mov v2.16b, v1.16b
27 2: ld1 {v1.4s}, [x0], #16
32 aese v0.16b, v1.16b
45 ld1 {v1.4s}, [x0], #16
49 mov v3.16b, v1.16b
51 0: mov v2.16b, v1.16b
55 2: ld1 {v1.4s}, [x0], #16
60 aesd v0.16b, v1.16b
[all …]
Daes-modes.S43 encrypt_block2x v0, v1, w3, x2, x6, w7
48 decrypt_block2x v0, v1, w3, x2, x6, w7
55 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
60 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
89 encrypt_block2x v0, v1, w3, x2, x6, w7
93 decrypt_block2x v0, v1, w3, x2, x6, w7
97 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
101 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
124 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
126 st1 {v0.16b-v1.16b}, [x0], #32
[all …]
Dchacha20-neon-core.S48 add v0.4s, v0.4s, v1.4s
54 eor v4.16b, v1.16b, v2.16b
55 shl v1.4s, v4.4s, #12
56 sri v1.4s, v4.4s, #20
59 add v0.4s, v0.4s, v1.4s
65 eor v4.16b, v1.16b, v2.16b
66 shl v1.4s, v4.4s, #7
67 sri v1.4s, v4.4s, #25
70 ext v1.16b, v1.16b, v1.16b, #4
77 add v0.4s, v0.4s, v1.4s
[all …]
Dcrct10dif-ce-core.S111 CPU_LE( rev64 v1.16b, v1.16b )
120 CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
170 fold64 v0, v1
200 fold16 v1, rk13
249 CPU_LE( rev64 v1.16b, v1.16b )
250 CPU_LE( ext v1.16b, v1.16b, v1.16b, #8 )
268 bsl v0.16b, v2.16b, v1.16b
/arch/s390/crypto/
Dcrc32be-vx.S103 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
104 VX %v1,%v0,%v1 /* V1 ^= CRC */
123 VGFMAG %v1,CONST_R1R2,%v1,%v5
137 VGFMAG %v1,CONST_R3R4,%v1,%v2
138 VGFMAG %v1,CONST_R3R4,%v1,%v3
139 VGFMAG %v1,CONST_R3R4,%v1,%v4
148 VGFMAG %v1,CONST_R3R4,%v1,%v2 /* Fold next data chunk */
166 VGFMG %v1,CONST_R5,%v1
175 VGFMG %v1,CONST_R6,%v1
196 VUPLLF %v2,%v1
[all …]
Dcrc32le-vx.S129 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
130 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
135 VX %v1,%v0,%v1 /* V1 ^= CRC */
157 VGFMAG %v1,CONST_R2R1,%v1,%v5
174 VGFMAG %v1,CONST_R4R3,%v1,%v2
175 VGFMAG %v1,CONST_R4R3,%v1,%v3
176 VGFMAG %v1,CONST_R4R3,%v1,%v4
185 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
216 VGFMG %v1,%v0,%v1
232 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
[all …]
/arch/powerpc/lib/
Dxor_vmx.c67 DEFINE(v1); in __xor_altivec_2()
72 LOAD(v1); in __xor_altivec_2()
74 XOR(v1, v2); in __xor_altivec_2()
75 STORE(v1); in __xor_altivec_2()
77 v1 += 4; in __xor_altivec_2()
85 DEFINE(v1); in __xor_altivec_3()
91 LOAD(v1); in __xor_altivec_3()
94 XOR(v1, v2); in __xor_altivec_3()
95 XOR(v1, v3); in __xor_altivec_3()
96 STORE(v1); in __xor_altivec_3()
[all …]
Dmemcpy_power7.S324 lvx v1,0,r4
326 stvx v1,0,r3
330 lvx v1,0,r4
333 stvx v1,0,r3
340 lvx v1,r4,r10
345 stvx v1,r3,r10
375 lvx v1,r4,r15
384 stvx v1,r3,r15
401 lvx v1,r4,r10
406 stvx v1,r3,r10
[all …]
Dcopyuser_power7.S379 err3; lvx v1,0,r4
381 err3; stvx v1,0,r3
385 err3; lvx v1,0,r4
388 err3; stvx v1,0,r3
395 err3; lvx v1,r4,r10
400 err3; stvx v1,r3,r10
430 err4; lvx v1,r4,r15
439 err4; stvx v1,r3,r15
456 err3; lvx v1,r4,r10
461 err3; stvx v1,r3,r10
[all …]
/arch/s390/include/asm/
Dvx-insn.h94 .ifc \vxr,%v1
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
202 .if \v1 & 0x10
224 .macro MRXB m v1 v2=0 v3=0 v4=0
226 RXB rxb, \v1, \v2, \v3, \v4
239 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
240 MRXB \m, \v1, \v2, \v3, \v4
248 VX_NUM v1, \vr
249 .word (0xE700 | ((v1&15) << 4))
251 MRXBOPC 0, 0x44, v1
[all …]
/arch/powerpc/boot/dts/fsl/
Dinterlaken-lac-portals.dtsi39 compatible = "fsl,interlaken-lac-portal-v1.0";
44 compatible = "fsl,interlaken-lac-portal-v1.0";
49 compatible = "fsl,interlaken-lac-portal-v1.0";
54 compatible = "fsl,interlaken-lac-portal-v1.0";
59 compatible = "fsl,interlaken-lac-portal-v1.0";
64 compatible = "fsl,interlaken-lac-portal-v1.0";
69 compatible = "fsl,interlaken-lac-portal-v1.0";
74 compatible = "fsl,interlaken-lac-portal-v1.0";
79 compatible = "fsl,interlaken-lac-portal-v1.0";
84 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
Dqoriq-raid1.0-0.dtsi36 compatible = "fsl,raideng-v1.0";
43 compatible = "fsl,raideng-v1.0-job-queue";
50 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
57 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
65 compatible = "fsl,raideng-v1.0-job-queue";
72 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
79 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
/arch/x86/lib/
Dx86-opcode-map.txt28 # (v1): this opcode only supports 128bit VEX.
349 # Many AVX instructions lack v1 superscript, according to Intel AVX-Prgramming
351 10: vmovups Vps,Wps | vmovupd Vpd,Wpd (66) | vmovss Vx,Hx,Wss (F3),(v1) | vmovsd Vx,Hx,Wsd (F2),(v1)
352 … vmovups Wps,Vps | vmovupd Wpd,Vpd (66) | vmovss Wss,Hx,Vss (F3),(v1) | vmovsd Wsd,Hx,Vsd (F2),(v1)
353 12: vmovlps Vq,Hq,Mq (v1) | vmovhlps Vq,Hq,Uq (v1) | vmovlpd Vq,Hq,Mq (66),(v1) | vmovsldup Vx,Wx (…
354 13: vmovlps Mq,Vq (v1) | vmovlpd Mq,Vq (66),(v1)
357 16: vmovhps Vdq,Hq,Mq (v1) | vmovlhps Vdq,Hq,Uq (v1) | vmovhpd Vdq,Hq,Mq (66),(v1) | vmovshdup Vx,W…
358 17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1)
382 …s Vps,Qpi | cvtpi2pd Vpd,Qpi (66) | vcvtsi2ss Vss,Hss,Ey (F3),(v1) | vcvtsi2sd Vsd,Hsd,Ey (F2),(v1)
384 …tps2pi Ppi,Wps | cvttpd2pi Ppi,Wpd (66) | vcvttss2si Gy,Wss (F3),(v1) | vcvttsd2si Gy,Wsd (F2),(v1)
[all …]
/arch/mips/kernel/
Dcpu-bugs64.c45 static inline void mult_sh_align_mod(long *v1, long *v2, long *w, in mult_sh_align_mod() argument
115 *v1 = lv1; in mult_sh_align_mod()
122 long v1[8], v2[8], w[8]; in check_mult_sh() local
136 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0); in check_mult_sh()
137 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1); in check_mult_sh()
138 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2); in check_mult_sh()
139 mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3); in check_mult_sh()
140 mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4); in check_mult_sh()
141 mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5); in check_mult_sh()
142 mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6); in check_mult_sh()
[all …]
/arch/powerpc/platforms/ps3/
Drepository.c66 u64 v1, u64 v2, const char *func, int line) in _dump_node() argument
73 pr_devel("%s:%d: v1: %016llx\n", func, line, v1); in _dump_node()
125 u64 v1; in read_node() local
134 result = lv1_read_repository_node(lpar_id, n1, n2, n3, n4, &v1, in read_node()
144 dump_node(lpar_id, n1, n2, n3, n4, v1, v2); in read_node()
147 *_v1 = v1; in read_node()
151 if (v1 && !_v1) in read_node()
153 __func__, __LINE__, v1); in read_node()
181 u64 v1 = 0; in ps3_repository_read_bus_type() local
187 &v1, NULL); in ps3_repository_read_bus_type()
[all …]
/arch/mips/netlogic/common/
Dreset.S108 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
109 mtcr v1, t1
111 mfcr v1, t1
112 andi v1, 0x1 /* wait for write_active == 0 */
113 bnez v1, 12b
116 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
117 mtcr v1, t1
119 mfcr v1, t1
120 andi v1, 0x1 /* wait for write_active == 0 */
121 bnez v1, 13b
[all …]
/arch/mips/include/asm/
Dstackframe.h60 mflhxu v1
61 LONG_S v1, PT_LO(sp)
62 mflhxu v1
63 LONG_S v1, PT_HI(sp)
64 mflhxu v1
65 LONG_S v1, PT_ACX(sp)
67 mfhi v1
77 LONG_S v1, PT_HI(sp)
78 mflo v1
85 LONG_S v1, PT_LO(sp)
[all …]
/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S165 vxor v1,v1,v1
269 vxor v1,v1,v9
324 vxor v1,v1,v9
355 vxor v1,v1,v9
371 vsldoi v1,v1,zeroes,4
401 vxor v17,v1,v9
430 lvx v1,off16,r3
440 VPMSUMW(v1,v17,v1)
501 1: vxor v0,v0,v1
519 vsldoi v1,v0,v0,8
[all …]
/arch/arm/boot/dts/
Dqcom-ipq8064.dtsi2 /dts-v1/;
20 enable-method = "qcom,kpss-acc-v1";
30 enable-method = "qcom,kpss-acc-v1";
142 compatible = "qcom,kpss-acc-v1";
147 compatible = "qcom,kpss-acc-v1";
164 compatible = "qcom,gsbi-v1.0.0";
177 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
187 compatible = "qcom,i2c-qup-v1.1.1";
202 compatible = "qcom,gsbi-v1.0.0";
215 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
[all …]
/arch/ia64/include/asm/sn/
Dsn_sal.h186 ret_stuff.v1 = 0; in ia64_sn_get_console_nasid()
208 ret_stuff.v1 = 0; in ia64_sn_get_master_baseio_nasid()
226 ret_stuff.v1 = 0; in ia64_sn_get_klconfig_addr()
242 ret_stuff.v1 = 0; in ia64_sn_console_getc()
264 ret_stuff.v1 = 0; in ia64_sn_console_readc()
282 ret_stuff.v1 = 0; in ia64_sn_console_putc()
299 ret_stuff.v1 = 0; in ia64_sn_console_putb()
319 ret_stuff.v1 = 0; in ia64_sn_plat_specific_err_print()
336 ret_stuff.v1 = 0; in ia64_sn_plat_cpei_handler()
353 ret_stuff.v1 = 0; in ia64_sn_plat_set_error_handling_features()
[all …]
/arch/mips/lib/
Dcsum_partial.S63 sltu v1, sum, reg; \
64 ADD sum, v1; \
71 sltu v1, sum, reg; \
72 addu sum, v1; \
274 dsll32 v1, sum, 0
275 daddu sum, v1
276 sltu v1, sum, v1
278 addu sum, v1
285 wsbh v1, sum
286 movn sum, v1, t7
[all …]
Dstrncpy_user.S39 move v1, a1
41 1: EX(lbu, v0, (v1), .Lfault\@)
43 1: EX(lbue, v0, (v1), .Lfault\@)
45 PTR_ADDIU v1, 1
/arch/um/drivers/
Dcow_user.c112 struct cow_header_v1 v1; member
295 if (n < offsetof(typeof(header->v1), backing_file)) { in read_cow_header()
300 magic = header->v1.magic; in read_cow_header()
302 version = header->v1.version; in read_cow_header()
304 version = be32toh(header->v1.version); in read_cow_header()
311 if (n < sizeof(header->v1)) { in read_cow_header()
316 *mtime_out = header->v1.mtime; in read_cow_header()
317 *size_out = header->v1.size; in read_cow_header()
318 *sectorsize_out = header->v1.sectorsize; in read_cow_header()
319 *bitmap_offset_out = sizeof(header->v1); in read_cow_header()
[all …]

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