| /arch/mips/sni/ |
| D | rm200.c | 167 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); in sni_rm200_disable_8259A_irq()
169 writeb(cached_master_mask, rm200_pic_master + PIC_IMR); in sni_rm200_disable_8259A_irq()
182 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); in sni_rm200_enable_8259A_irq()
184 writeb(cached_master_mask, rm200_pic_master + PIC_IMR); in sni_rm200_enable_8259A_irq()
194 writeb(0x0B, rm200_pic_master + PIC_CMD); in sni_rm200_i8259A_irq_real()
196 writeb(0x0A, rm200_pic_master + PIC_CMD); in sni_rm200_i8259A_irq_real()
199 writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */ in sni_rm200_i8259A_irq_real()
201 writeb(0x0A, rm200_pic_slave + PIC_CMD); in sni_rm200_i8259A_irq_real()
240 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); in sni_rm200_mask_and_ack_8259A()
241 writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD); in sni_rm200_mask_and_ack_8259A()
[all …]
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| /arch/m68k/coldfire/ |
| D | m528x.c | 92 writeb(port, MCFGPIO_PUAPAR); in m528x_uarts_init()
104 writeb(0xc0, MCFGPIO_PEHLPAR); in m528x_fec_init()
112 writeb(0, 0x30000007); in wildfire_halt()
113 writeb(0x2, 0x30000007); in wildfire_halt()
126 writeb(readb(MCFGPIO_PDDR_E) | (1 << 5), MCFGPIO_PDDR_E); in wildfiremod_halt()
129 writeb(readb(MCFGPIO_PODR_E) & ~(1 << 5), MCFGPIO_PODR_E); in wildfiremod_halt()
130 writeb(readb(MCFGPIO_PODR_E) | (1 << 5), MCFGPIO_PODR_E); in wildfiremod_halt()
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| D | m527x.c | 68 writeb(0x1f, MCFGPIO_PAR_QSPI); in m527x_qspi_init()
92 writeb(par, MCFGPIO_PAR_FECI2C); in m527x_i2c_init()
128 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); in m527x_fec_init()
135 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); in m527x_fec_init()
141 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); in m527x_fec_init()
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| D | m520x.c | 127 writeb(0x3f, MCF_GPIO_PAR_QSPI); in m520x_qspi_init()
146 writeb(par, MCF_GPIO_PAR_FECI2C); in m520x_i2c_init()
168 writeb(par2, MCF_GPIO_PAR_FECI2C); in m520x_uarts_init()
179 writeb(v | 0xf0, MCF_GPIO_PAR_FEC); in m520x_fec_init()
182 writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C); in m520x_fec_init()
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| D | m523x.c | 64 writeb(0x1f, MCFGPIO_PAR_QSPI); in m523x_qspi_init()
83 writeb(par, MCFGPIO_PAR_FECI2C); in m523x_i2c_init()
92 writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C); in m523x_fec_init()
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| D | m53xx.c | 186 writeb(r, MCFGPIO_PAR_FECI2C); in m53xx_i2c_init()
208 writeb(v, MCFGPIO_PAR_FECI2C); in m53xx_fec_init()
212 writeb(v, MCFGPIO_PAR_FEC); in m53xx_fec_init()
339 writeb(0x3E, MCFGPIO_PAR_CS); in fbcs_init()
469 writeb(0x00, MCFGPIO_PAR_TIMER); in gpio_init()
470 writeb(0x08, MCFGPIO_PDDR_TIMER); in gpio_init()
471 writeb(0x00, MCFGPIO_PCLRR_TIMER); in gpio_init()
523 writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV), in clock_pll()
526 writeb(mfd, MCF_PLL_PFDR); in clock_pll()
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| D | m525x.c | 59 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, in m525x_qspi_init()
71 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m525x_i2c_init()
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| D | m5249.c | 85 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0, in m5249_qspi_init()
99 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0, in m5249_i2c_init()
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| /arch/mips/txx9/rbtx4938/ |
| D | setup.c | 33 writeb(1, rbtx4938_softresetlock_addr); in rbtx4938_machine_restart()
34 writeb(1, rbtx4938_sfvol_addr); in rbtx4938_machine_restart()
35 writeb(1, rbtx4938_softreset_addr); in rbtx4938_machine_restart()
54 writeb(0, rbtx4938_pcireset_addr); in rbtx4938_pci_setup()
63 writeb(1, rbtx4938_pcireset_addr); in rbtx4938_pci_setup()
72 writeb(0, rbtx4938_pcireset_addr); in rbtx4938_pci_setup()
79 writeb(1, rbtx4938_pcireset_addr); in rbtx4938_pci_setup()
202 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, in rbtx4938_mem_setup()
206 writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, in rbtx4938_mem_setup()
209 writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), in rbtx4938_mem_setup()
[all …]
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| D | irq.c | 89 writeb(v, rbtx4938_imask_addr); in toshiba_rbtx4938_irq_ioc_enable()
99 writeb(v, rbtx4938_imask_addr); in toshiba_rbtx4938_irq_ioc_disable()
149 writeb(0, rbtx4938_imask_addr); in rbtx4938_irq_setup()
152 writeb(0, rbtx4938_softint_addr); in rbtx4938_irq_setup()
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| /arch/mips/txx9/rbtx4927/ |
| D | setup.c | 75 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
84 writeb(0, rbtx4927_pcireset_addr); in tx4927_pci_setup()
93 writeb(1, rbtx4927_pcireset_addr); in tx4927_pci_setup()
100 writeb(0, rbtx4927_pcireset_addr); in tx4927_pci_setup()
122 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
131 writeb(0, rbtx4927_pcireset_addr); in tx4937_pci_setup()
140 writeb(1, rbtx4927_pcireset_addr); in tx4937_pci_setup()
147 writeb(0, rbtx4927_pcireset_addr); in tx4937_pci_setup()
190 writeb(1, rbtx4927_softresetlock_addr); in toshiba_rbtx4927_restart()
197 writeb(1, rbtx4927_softreset_addr); in toshiba_rbtx4927_restart()
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| D | irq.c | 136 writeb(v, rbtx4927_imask_addr); in toshiba_rbtx4927_irq_ioc_enable()
145 writeb(v, rbtx4927_imask_addr); in toshiba_rbtx4927_irq_ioc_disable()
161 writeb(0, rbtx4927_imask_addr); in toshiba_rbtx4927_irq_ioc_init()
163 writeb(0, rbtx4927_softint_addr); in toshiba_rbtx4927_irq_ioc_init()
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| /arch/mips/txx9/rbtx4939/ |
| D | irq.c | 26 writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr); in rbtx4939_ioc_irq_unmask()
33 writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr); in rbtx4939_ioc_irq_mask()
81 writeb(0, rbtx4939_ien_addr); in rbtx4939_irq_setup()
84 writeb(0, rbtx4939_softint_addr); in rbtx4939_irq_setup()
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| /arch/nios2/boot/compressed/ |
| D | console.c | 43 writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG); in jtag_putc()
51 writeb(ch, uartbase + ALTERA_JTAGUART_DATA_REG); in jtag_putc()
86 writeb(ch, uartbase + ALTERA_UART_TXDATA_REG); in uart_putc()
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| /arch/m68k/include/asm/ |
| D | vga.h | 18 #undef writeb
25 #define writeb raw_outb macro
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| D | ide.h | 45 #undef writeb
52 #define writeb(val, port) out_8(port, val) macro
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| /arch/mips/jz4740/ |
| D | reset.c | 50 writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); in jz4740_restart()
56 writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE); in jz4740_restart()
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| /arch/ia64/include/asm/ |
| D | smp.h | 98 writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */ in min_xtp()
105 writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */ in normal_xtp()
112 writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */ in max_xtp()
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| /arch/sparc/include/asm/ |
| D | io_64.h | 155 #define writeb writeb macro
156 #define writeb_relaxed writeb
157 static inline void writeb(u8 b, volatile void __iomem *addr) in writeb() function
216 writeb(b, (volatile void __iomem *)addr); in outb()
336 writeb(c, d); in memset_io()
387 writeb(tmp, d); in memcpy_toio()
417 #define iowrite8 writeb
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| /arch/mn10300/include/asm/ |
| D | io.h | 51 static inline void writeb(u8 b, volatile void __iomem *addr) in writeb() function
66 #define __raw_writeb writeb
70 #define writeb_relaxed writeb
85 return writeb(b, (volatile void __iomem *) addr); in outb_local()
105 return writeb(b, (volatile void __iomem *) addr); in outb()
196 #define iowrite8(v, addr) writeb((v), (addr))
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| /arch/m32r/include/asm/ |
| D | io.h | 162 #define writeb(val, addr) _writeb((val), (unsigned long)(addr)) macro
165 #define __raw_writeb writeb
168 #define writeb_relaxed writeb
175 #define iowrite8 writeb
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| /arch/mips/sgi-ip22/ |
| D | ip22-time.c | 48 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CLAT, &sgint->tcword); in dosample()
55 writeb(SGINT_TCWORD_CNT2 | SGINT_TCWORD_CALL | SGINT_TCWORD_MSWST, in dosample()
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| /arch/arm/kernel/ |
| D | io.c | 66 writeb(*f, to); in _memcpy_toio()
81 writeb(c, dst); in _memset_io()
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| /arch/mips/sibyte/swarm/ |
| D | setup.c | 176 writeb(' ', reg); in setleds()
178 writeb(str[i], reg); in setleds()
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| /arch/arm/mach-footbridge/ |
| D | ebsa285.c | 58 writeb(hw_led_state, xbus); in ebsa285_led_set()
82 writeb(hw_led_state, xbus); in ebsa285_leds_init()
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