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Searched refs:ARRAY_2D_TILED_THIN1 (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c417 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
452 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
480 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
[all …]
Dgfx_v8_0.c2085 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2089 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2093 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2097 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2101 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2119 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2131 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2179 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2256 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2260 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
[all …]
Dgfx_v7_0.c1052 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1056 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1060 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1064 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1068 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1085 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1097 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1145 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1219 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1223 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
[all …]
Dsid.h1182 # define ARRAY_2D_TILED_THIN1 4 macro
/drivers/gpu/drm/radeon/
Dsi.c2516 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2525 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2534 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2543 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2561 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2570 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2579 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2606 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2615 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2624 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
[all …]
Dcik.c2370 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2374 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2378 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2382 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2386 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2406 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2421 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2436 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2513 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2517 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
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Devergreen_cs.c96 return ARRAY_2D_TILED_THIN1; in evergreen_cs_get_aray_mode()
311 case ARRAY_2D_TILED_THIN1: in evergreen_surface_check()
326 case ARRAY_2D_TILED_THIN1: in evergreen_surface_value_conv_check()
883 case ARRAY_2D_TILED_THIN1: in evergreen_cs_track_validate_texture()
Dsid.h1184 # define ARRAY_2D_TILED_THIN1 4 macro
Dcikd.h1224 # define ARRAY_2D_TILED_THIN1 4 macro
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dgmc_8_1_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_0_enum.h81 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_2_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_3_enum.h85 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_1_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dbif_5_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Ddce_10_0_enum.h613 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h541 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Duvd_5_0_enum.h51 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h223 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Doss_3_0_1_enum.h924 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Doss_3_0_enum.h337 ARRAY_2D_TILED_THIN1 = 0x4, enumerator

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