1 /* 2 * Copyright (C) 2012-2017 ARM Limited or its affiliates. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 /* \file ssi_driver.h 18 * ARM CryptoCell Linux Crypto Driver 19 */ 20 21 #ifndef __SSI_DRIVER_H__ 22 #define __SSI_DRIVER_H__ 23 24 #include "ssi_config.h" 25 #ifdef COMP_IN_WQ 26 #include <linux/workqueue.h> 27 #else 28 #include <linux/interrupt.h> 29 #endif 30 #include <linux/dma-mapping.h> 31 #include <crypto/algapi.h> 32 #include <crypto/internal/skcipher.h> 33 #include <crypto/aes.h> 34 #include <crypto/sha.h> 35 #include <crypto/aead.h> 36 #include <crypto/authenc.h> 37 #include <crypto/hash.h> 38 #include <linux/version.h> 39 #include <linux/clk.h> 40 41 /* Registers definitions from shared/hw/ree_include */ 42 #include "dx_reg_base_host.h" 43 #include "dx_host.h" 44 #include "cc_regs.h" 45 #include "dx_reg_common.h" 46 #include "cc_hal.h" 47 #define CC_SUPPORT_SHA DX_DEV_SHA_MAX 48 #include "cc_crypto_ctx.h" 49 #include "ssi_sysfs.h" 50 #include "hash_defs.h" 51 #include "cc_hw_queue_defs.h" 52 #include "ssi_sram_mgr.h" 53 54 #define DRV_MODULE_VERSION "3.0" 55 56 #define SSI_DEV_NAME_STR "cc715ree" 57 #define CC_COHERENT_CACHE_PARAMS 0xEEE 58 59 #define SSI_CC_HAS_AES_CCM 1 60 #define SSI_CC_HAS_AES_GCM 1 61 #define SSI_CC_HAS_AES_XTS 1 62 #define SSI_CC_HAS_AES_ESSIV 1 63 #define SSI_CC_HAS_AES_BITLOCKER 1 64 #define SSI_CC_HAS_AES_CTS 1 65 #define SSI_CC_HAS_MULTI2 0 66 #define SSI_CC_HAS_CMAC 1 67 68 #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ 69 (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | (1 << DX_AXIM_CFG_COMPMASK_BIT_SHIFT)) 70 71 #define SSI_AXI_ERR_IRQ_MASK (1 << DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT) 72 73 #define SSI_COMP_IRQ_MASK (1 << DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT) 74 75 /* TEE FIPS status interrupt */ 76 #define SSI_GPR0_IRQ_MASK (1 << DX_HOST_IRR_GPR0_BIT_SHIFT) 77 78 #define SSI_CRA_PRIO 3000 79 80 #define MIN_HW_QUEUE_SIZE 50 /* Minimum size required for proper function */ 81 82 #define MAX_REQUEST_QUEUE_SIZE 4096 83 #define MAX_MLLI_BUFF_SIZE 2080 84 #define MAX_ICV_NENTS_SUPPORTED 2 85 86 /* Definitions for HW descriptors DIN/DOUT fields */ 87 #define NS_BIT 1 88 #define AXI_ID 0 89 /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID 90 * field in the HW descriptor. The DMA engine +8 that value. 91 */ 92 93 /* Logging macros */ 94 #define SSI_LOG(level, format, ...) \ 95 printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__) 96 #define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__) 97 #define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__) 98 #define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__) 99 #define SSI_LOG_INFO(format, ...) SSI_LOG(KERN_INFO, format, ##__VA_ARGS__) 100 #ifdef CC_DEBUG 101 #define SSI_LOG_DEBUG(format, ...) SSI_LOG(KERN_DEBUG, format, ##__VA_ARGS__) 102 #else /* Debug log messages are removed at compile time for non-DEBUG config. */ 103 #define SSI_LOG_DEBUG(format, ...) do {} while (0) 104 #endif 105 106 #define MIN(a, b) (((a) < (b)) ? (a) : (b)) 107 #define MAX(a, b) (((a) > (b)) ? (a) : (b)) 108 109 #define SSI_MAX_IVGEN_DMA_ADDRESSES 3 110 struct ssi_crypto_req { 111 void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base); 112 void *user_arg; 113 dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; 114 /* For the first 'ivgen_dma_addr_len' addresses of this array, 115 * generated IV would be placed in it by send_request(). 116 * Same generated IV for all addresses! 117 */ 118 unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */ 119 unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */ 120 struct completion seq_compl; /* request completion */ 121 }; 122 123 /** 124 * struct ssi_drvdata - driver private data context 125 * @cc_base: virt address of the CC registers 126 * @irq: device IRQ number 127 * @irq_mask: Interrupt mask shadow (1 for masked interrupts) 128 * @fw_ver: SeP loaded firmware version 129 */ 130 struct ssi_drvdata { 131 struct resource *res_mem; 132 struct resource *res_irq; 133 void __iomem *cc_base; 134 unsigned int irq; 135 u32 irq_mask; 136 u32 fw_ver; 137 /* Calibration time of start/stop 138 * monitor descriptors 139 */ 140 u32 monitor_null_cycles; 141 struct platform_device *plat_dev; 142 ssi_sram_addr_t mlli_sram_addr; 143 struct completion icache_setup_completion; 144 void *buff_mgr_handle; 145 void *hash_handle; 146 void *aead_handle; 147 void *blkcipher_handle; 148 void *request_mgr_handle; 149 void *fips_handle; 150 void *ivgen_handle; 151 void *sram_mgr_handle; 152 u32 inflight_counter; 153 struct clk *clk; 154 bool coherent; 155 }; 156 157 struct ssi_crypto_alg { 158 struct list_head entry; 159 int cipher_mode; 160 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 161 int auth_mode; 162 struct ssi_drvdata *drvdata; 163 struct crypto_alg crypto_alg; 164 struct aead_alg aead_alg; 165 }; 166 167 struct ssi_alg_template { 168 char name[CRYPTO_MAX_ALG_NAME]; 169 char driver_name[CRYPTO_MAX_ALG_NAME]; 170 unsigned int blocksize; 171 u32 type; 172 union { 173 struct ablkcipher_alg ablkcipher; 174 struct aead_alg aead; 175 struct blkcipher_alg blkcipher; 176 struct cipher_alg cipher; 177 struct compress_alg compress; 178 } template_u; 179 int cipher_mode; 180 int flow_mode; /* Note: currently, refers to the cipher mode only. */ 181 int auth_mode; 182 struct ssi_drvdata *drvdata; 183 }; 184 185 struct async_gen_req_ctx { 186 dma_addr_t iv_dma_addr; 187 enum drv_crypto_direction op_type; 188 }; 189 190 #ifdef DX_DUMP_BYTES 191 void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); 192 #else 193 #define dump_byte_array(name, array, size) do { \ 194 } while (0); 195 #endif 196 197 int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); 198 void fini_cc_regs(struct ssi_drvdata *drvdata); 199 int cc_clk_on(struct ssi_drvdata *drvdata); 200 void cc_clk_off(struct ssi_drvdata *drvdata); 201 202 #endif /*__SSI_DRIVER_H__*/ 203 204