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Searched refs:BIT15 (Results 1 – 19 of 19) sorted by relevance

/drivers/staging/emxx_udc/
Demxx_udc.h82 #define BIT15 0x00008000 macro
127 #define SOF_STATUS BIT15
156 #define EP7_INT BIT15
183 #define EP7_EN BIT15
224 #define EP0_OUT_NAK_INT BIT15
241 #define EP0_STATUS_RW_BIT (BIT16 | BIT15 | BIT11 | 0xFF)
245 #define EP0_OUT_NAK_EN BIT15
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h190 #define CAM_VALID BIT15
223 #define IMR_TXFOVW BIT15
256 #define TPPoll_StopHCCA BIT15
386 #define RRSR_MCS3 BIT15
Drtl_cam.c126 usConfig |= BIT15 | (KeyType<<2); in rtl92e_set_key()
128 usConfig |= BIT15 | (KeyType<<2) | KeyIndex; in rtl92e_set_key()
/drivers/staging/rtl8723bs/include/
Drtl8723b_spec.h221 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is …
249 #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */
Dhal_com_reg.h631 #define RRSR_MCS3 BIT15
741 #define CAM_VALID BIT15
797 #define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */
815 #define IMR_TSF_BIT32_TOGGLE BIT15
845 #define PHIMR_HSISR_IND_ON BIT15
896 #define UHIMR_HSISR_IND BIT15
951 #define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set…
980 #define IMR_BCNDOK2_88E BIT15 /* Beacon Queue DMA OK Interrup 2 */
1044 #define RCR_RSVD_BIT15 BIT15 /* Reserved */
Dosdep_service.h44 #define BIT15 0x00008000 macro
/drivers/staging/rtlwifi/btcoexist/
Dhalbt_precomp.h67 #define BIT15 0x00008000 macro
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h69 #define BIT15 0x00008000 macro
/drivers/staging/rtl8723bs/hal/
DHal8723BReg.h395 #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is se…
423 #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */
Dodm_debug.h84 #define ODM_COMP_CFO_TRACKING BIT15
Dhal_com.c1742 PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); in rtw_bb_rf_gain_offset()
/drivers/staging/rtl8192e/
Drtl819x_Qos.h33 #define BIT15 0x00008000 macro
/drivers/tty/
Dsynclink.c558 #define MISCSTATUS_RXC_LATCHED BIT15
578 #define SICR_RXC_ACTIVE BIT15
580 #define SICR_RXC (BIT15|BIT14)
635 #define DICR_MASTER BIT15
1840 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); in shutdown()
4695 RegValue |= BIT15; in usc_set_sdlc_mode()
4697 RegValue |= BIT15 | BIT14; in usc_set_sdlc_mode()
4739 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break; in usc_set_sdlc_mode()
4740 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 | BIT13; break; in usc_set_sdlc_mode()
4741 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14; break; in usc_set_sdlc_mode()
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Dsynclink_gt.c219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
2126 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8)); in isr_rxdata()
4227 val = BIT15 + BIT14 + BIT0; in async_mode()
4279 val |= BIT15 + BIT13; in sync_mode()
4282 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()
4354 val |= BIT15 + BIT13; in sync_mode()
4357 case MGSL_MODE_BISYNC: val |= BIT15; break; in sync_mode()
4463 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0); in sync_mode()
/drivers/net/ethernet/cirrus/
Dcs89x0.h464 #define BIT15 0x8000 macro
/drivers/scsi/
Ddc395x.h61 #define BIT15 0x00008000 macro
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h395 #define RRSR_MCS3 BIT15
/drivers/scsi/lpfc/
Dlpfc_hw4.h711 #define LPFC_SLI4_INTR15 BIT15
/drivers/char/pcmcia/
Dsynclink_cs.c290 #define IRQ_BREAK_ON BIT15 // rx break detected