Home
last modified time | relevance | path

Searched refs:BIT4 (Results 1 – 25 of 49) sorted by relevance

12

/drivers/staging/rtl8723bs/include/
DHal8723BPwrSeq.h45 …MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 …
48 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* d…
54 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disabl…
83 …PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x0…
84 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
85 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b…
87 …FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:1…
97 …MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b…
98 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] …
104 …PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:1…
[all …]
Dhal_com_reg.h540 #define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9…
541 #define Cmd9346CR_9356SEL BIT4
620 #define RRSR_6M BIT4
645 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4
808 #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */
856 #define PHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */
907 #define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */
961 #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */
1019 #define StopMgt BIT4
1056 #define RCR_ADD3 BIT4 /* Accept address 3 match packet */
[all …]
Drtl8723b_spec.h230 #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
[all …]
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h111 #define EPROM_CMD_9356SEL BIT4
215 #define SCR_SKByA2 BIT4
234 #define IMR_BKDOK BIT4
245 #define TPPoll_BQ BIT4
285 #define AcmHw_BeqStatus BIT4
375 #define RRSR_6M BIT4
Drtl_pci.c37 tmp |= BIT4; in _rtl92e_parse_pci_configuration()
/drivers/scsi/
Ddc395x.h72 #define BIT4 0x00000010 macro
133 #define PARITY_ERROR BIT4
140 #define ENABLE_TIMER BIT4
178 #define WIDE_NEGO_STATE BIT4
634 #define NO_SEEK BIT4
/drivers/video/fbdev/via/
Ddvi.c75 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
340 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
361 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4); in dvi_patch_skew_dvp0()
Dhw.c962 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
1728 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1732 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1735 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1740 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1743 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
2076 BIT4); in viafb_set_dpa_gfx()
Dshare.h32 #define BIT4 0x10 macro
/drivers/staging/rtlwifi/btcoexist/
Dhalbt_precomp.h56 #define BIT4 0x00000010 macro
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h58 #define BIT4 0x00000010 macro
Dhalbtc8192e2ant.h31 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
Dhalbtcoutsrc.h117 #define ALGO_TRACE_FW BIT4
129 #define WIFI_P2P_GC_CONNECTED BIT4
Dhalbtc8821a1ant.h33 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
Dhalbtc8723b2ant.h34 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
Dhalbtc8821a2ant.h33 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
/drivers/staging/rtl8723bs/hal/
Dodm.h443 ODM_BB_RSSI_MONITOR = BIT4,
506 ODM_RF_RX_A = BIT4,
555 ODM_AP_MODE = BIT4,
569 ODM_WM_N5G = BIT4,
Dodm_debug.h73 #define ODM_COMP_RSSI_MONITOR BIT4
DHalHWImg8723B_MAC.c24 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
DHalBtc8723b2Ant.h19 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
DHalBtcOutSrc.h105 #define ALGO_TRACE_FW BIT4
117 #define WIFI_P2P_GC_CONNECTED BIT4
DHalBtc8723b1Ant.h19 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
/drivers/staging/rtl8192e/
Drtl819x_Qos.h22 #define BIT4 0x00000010 macro
/drivers/tty/
Dsynclink.c492 #define RECEIVE_DATA BIT4
509 #define RXSTATUS_RXBOUND BIT4
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
569 #define MISCSTATUS_CTS BIT4
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5|BIT4)
629 #define TXSTATUS_EOF BIT4
4712 RegValue |= BIT4; in usc_set_sdlc_mode()
4984 RegValue |= BIT4; /* enable BRG1 */ in usc_set_sdlc_mode()
[all …]

12