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Searched refs:CGTS_SM_CTRL_REG (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/radeon/
Dtrinityd.h224 #define CGTS_SM_CTRL_REG 0x9150 macro
Dni.c1162 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG); in cayman_gpu_init()
1164 WREG32(CGTS_SM_CTRL_REG, OVERRIDE); in cayman_gpu_init()
1165 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); in cayman_gpu_init()
Drv770d.h310 #define CGTS_SM_CTRL_REG 0x9150 macro
Dtrinity_dpm.c416 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE); in trinity_mg_clockgating_enable()
418 WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE); in trinity_mg_clockgating_enable()
Dnid.h419 #define CGTS_SM_CTRL_REG 0x9150 macro
Dcypress_dpm.c195 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg); in cypress_mg_clock_gating_enable()
216 WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0); in cypress_mg_clock_gating_enable()
Dsid.h1141 #define CGTS_SM_CTRL_REG 0x9150 macro
Dcikd.h1655 #define CGTS_SM_CTRL_REG 0x3c000 macro
Dsi.c5397 orig = data = RREG32(CGTS_SM_CTRL_REG); in si_enable_mgcg()
5400 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5432 orig = data = RREG32(CGTS_SM_CTRL_REG); in si_enable_mgcg()
5435 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
Devergreend.h340 #define CGTS_SM_CTRL_REG 0x9150 macro
Dcik.c6111 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6123 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6143 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6146 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
Drv770_dpm.c160 WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT); in rv770_mg_clock_gating_enable()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h1140 #define CGTS_SM_CTRL_REG 0x2454 macro