| /drivers/gpu/drm/radeon/ |
| D | rv740d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | rv730d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | rs780d.h | 26 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | rs780_dpm.c | 211 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv()
986 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_debugfs_print_current_performance_level()
1008 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in rs780_dpm_get_current_sclk()
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| D | r600_dpm.c | 323 WREG32_P(CG_SPLL_FUNC_CNTL, SPLL_BYPASS_EN, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
325 WREG32_P(CG_SPLL_FUNC_CNTL, 0, ~SPLL_BYPASS_EN); in r600_enable_spll_bypass()
333 if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS) in r600_wait_for_spll_change()
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| D | rv740_dpm.c | 290 RREG32(CG_SPLL_FUNC_CNTL); in rv740_read_clock_registers()
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| D | rv730_dpm.c | 203 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
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| D | rv770d.h | 89 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | si.c | 3987 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_set_clk_bypass_mode()
3989 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
4018 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4020 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4022 tmp = RREG32(CG_SPLL_FUNC_CNTL); in si_spll_powerdown()
4024 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
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| D | nid.h | 538 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | sid.h | 85 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | cikd.h | 250 #define CG_SPLL_FUNC_CNTL 0xC0500140 macro
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| D | evergreend.h | 74 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | r600d.h | 1270 #define CG_SPLL_FUNC_CNTL 0x600 macro
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| D | rv770_dpm.c | 1522 RREG32(CG_SPLL_FUNC_CNTL); in rv770_read_clock_registers()
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| D | ni_dpm.c | 1183 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in ni_read_clock_registers()
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| D | ci_dpm.c | 1851 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()
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| D | si_dpm.c | 3570 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
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| /drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | iceland_smc.c | 669 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
671 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
1334 CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0); in iceland_populate_smc_acpi_level()
1336 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
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| D | fiji_smc.c | 651 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
653 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_calculate_sclk_params()
1132 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
1134 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in fiji_populate_smc_acpi_level()
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| D | tonga_smc.c | 474 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
476 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
1125 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
1127 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, in tonga_populate_smc_acpi_level()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 87 #define CG_SPLL_FUNC_CNTL 0x180 macro
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| D | si_dpm.c | 4028 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); in si_read_clock_registers()
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