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Searched refs:DDR (Results 1 – 11 of 11) sorted by relevance

/drivers/gpio/
Dgpio-mb86s7x.c34 #define DDR(x) (0x10 + x / 8 * 4) macro
91 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
93 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
116 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
118 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
/drivers/memory/
DKconfig19 bool "Atmel (Multi-port DDR-)SDRAM Controller"
24 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
25 Starting with the at91sam9g45, this controller supports SDR, DDR and
26 LP-DDR memories.
54 select DDR
/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/
Dhive_isp_css_host_ids_hrt.h75 #define DDR testbench_ddram macro
77 #define XMEM DDR
/drivers/mtd/lpddr/
DKconfig9 flash chips. Synonymous with Mobile-DDR. It is a new standard for
10 DDR memories, intended for battery-operated systems.
/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/
Dhive_isp_css_host_ids_hrt.h101 #define DDR testbench_ddram macro
103 #define XMEM DDR
/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/
Dhive_isp_css_host_ids_hrt.h101 #define DDR testbench_ddram macro
103 #define XMEM DDR
/drivers/pinctrl/tegra/
Dpinctrl-tegra30.c2211 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2212 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2213 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2270 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2271 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2272 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2273 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2274 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2275 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2276 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
/drivers/devfreq/event/
DKconfig39 (DDR Monitor Module) driver to count ddr load.
/drivers/edac/
DKconfig256 tristate "Freescale Layerscape DDR"
447 tristate "Synopsys DDR Memory Controller"
450 Support for error detection and correction on the Synopsys DDR
/drivers/mmc/host/
Domap_hsmmc.c99 #define DDR (1 << 19) macro
667 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width()
669 con &= ~DDR; in omap_hsmmc_set_bus_width()
/drivers/hid/
DKconfig870 Note that DDR (Dance Dance Revolution) mode is not supported, nor