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Searched refs:DISP1_GAP_MCHG_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Drv6xxd.h140 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
Drv770d.h265 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
Dsid.h311 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
Drv770_dpm.c882 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv770_enable_display_gap()
1346 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv770_program_display_gap()
Devergreend.h203 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
Dcypress_dpm.c1736 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in cypress_enable_display_gap()
Drv6xx_dpm.c1185 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in rv6xx_program_display_gap()
Dsi_dpm.c3805 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in si_enable_display_gap()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h313 # define DISP1_GAP_MCHG_MASK (3 << 24) macro
Dsi_dpm.c4269 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); in si_enable_display_gap()