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Searched refs:DISPLAY_PLANE_ENABLE (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/gma500/
Dmdfld_intel_display.c254 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_disable_crtc()
256 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_disable_crtc()
366 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in mdfld_crtc_dpms()
368 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
394 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
410 temp | DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
442 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in mdfld_crtc_dpms()
444 temp & ~DISPLAY_PLANE_ENABLE); in mdfld_crtc_dpms()
860 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
Doaktrail_hdmi.c358 dspcntr |= DISPLAY_PLANE_ENABLE; in oaktrail_crtc_hdmi_mode_set()
392 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_hdmi_dpms()
393 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
460 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_hdmi_dpms()
461 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); in oaktrail_crtc_hdmi_dpms()
Doaktrail_crtc.c279 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in oaktrail_crtc_dpms()
281 temp | DISPLAY_PLANE_ENABLE, in oaktrail_crtc_dpms()
305 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in oaktrail_crtc_dpms()
307 temp & ~DISPLAY_PLANE_ENABLE, i); in oaktrail_crtc_dpms()
Dgma_display.c237 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { in gma_crtc_dpms()
239 temp | DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
284 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { in gma_crtc_dpms()
286 temp & ~DISPLAY_PLANE_ENABLE); in gma_crtc_dpms()
Dmdfld_device.c357 PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr); in mdfld_restore_display_registers()
Dpsb_intel_display.c212 dspcntr |= DISPLAY_PLANE_ENABLE; in psb_intel_crtc_mode_set()
Dpsb_intel_reg.h636 #define DISPLAY_PLANE_ENABLE (1 << 31) macro
Dcdv_intel_display.c733 dspcntr |= DISPLAY_PLANE_ENABLE; in cdv_intel_crtc_mode_set()
/drivers/gpu/drm/i915/
Dintel_display.c3164 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; in i9xx_plane_ctl()
3357 ret = I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE; in i9xx_plane_get_hw_state()
7495 if (!(val & DISPLAY_PLANE_ENABLE)) in i9xx_get_initial_plane_config()
8633 if (!(val & DISPLAY_PLANE_ENABLE)) in ironlake_get_initial_plane_config()
14741 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
14742 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
14743 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
14763 return (val & DISPLAY_PLANE_ENABLE) == 0 || in intel_plane_mapping_ok()
Di915_reg.h5877 #define DISPLAY_PLANE_ENABLE (1<<31) macro